1. Apr 11, 2020
  2. Apr 08, 2020
    • Albert Magyar's avatar
      Fix dynamic SubAccess of zero-length vectors (#1450) · 1a03e635
      Albert Magyar authored
      * Fix dynamic SubAccess of zero-length vectors
      
      * Fixes #230
      * Add new ZeroLengthVecs pass that occurs before RemoveAccesses
      * Include this in stage.Forms.MidForm
      * Add to High->Mid order in compiler test based on @seldridge feedback
      
      * Use validif to produce out-of-bounds value in ZeroLengthVecs
      
      * Update scaladoc
      
      * Fix test imports
      1a03e635
  3. Apr 07, 2020
  4. Apr 06, 2020
  5. Apr 03, 2020
  6. Mar 31, 2020
  7. Mar 27, 2020
  8. Mar 26, 2020
  9. Mar 24, 2020
  10. Mar 22, 2020
  11. Mar 18, 2020
  12. Mar 17, 2020
  13. Mar 15, 2020
  14. Mar 14, 2020
  15. Mar 13, 2020
    • John's Brew's avatar
      Add Support for FPGA Bitstream Preset-registers (#1050) · 5c0c0018
      John's Brew authored
      
      
      Introduce Preset Register Specialized Emission
      - Introduce EmissionOption trait
      - Introduce PresetAnnotation & PresetRegAnnotation
      - Enable the collection of Annotations in the Emitter
      - Introduce collection mechanism for EmissionOptions in the Emitter
      - Add PropagatePresetAnnotation transform to annotate register for emission and clean-up the useless reset tree (no DCE involved)
      - Add corresponding tests spec and tester
      
      Co-authored-by: default avatarJack Koenig <koenig@sifive.com>
      5c0c0018