Commits · fix-recursive-module-132 · github.com / freechipsproject / firrtl

Jun 10, 2016
- Recursive modules tests now work · 45dc60c7
  chick authored Jun 09, 2016
  
  45dc60c7
Jun 04, 2016
- Recursive modules now detected, have not yet been able to get test to work · 3fb11f46
  chick authored Jun 03, 2016
  
  3fb11f46
May 25, 2016
- Update sbt-antlr4 URL · 26694d34
  Andrew Waterman authored May 24, 2016
```
This is a good reason not to rely on published JARs...
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  26694d34
- Added Errors class and fixed tests. · f9e8895b
  azidar authored May 24, 2016
```
Canonicalizes catching/throwing PassExceptions.
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  f9e8895b
- add better type mismatch error message · 243ff24f
  Colin Schmidt authored Apr 19, 2016
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also check for it int unittest
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  243ff24f
- Add integration test for single-ported memory · 89cbd832
  jackkoenig authored Apr 27, 2016
  
  89cbd832
- Remove nested AND in creation of readwrite ports for mems. · b9bf7ad1
  jackkoenig authored Apr 27, 2016
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Fixes #147
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  b9bf7ad1
- Fix LowerTypes to check for wmode instead of rmode · 44e079a0
  jackkoenig authored Apr 27, 2016
  
  44e079a0
May 13, 2016
- Restructured Compiler to use Transforms. Added an InlineInstance pass. · f07baed2
  Adam Izraelevitz authored May 02, 2016
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Transforms are new unit of modularity within the compiler.
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  f07baed2
May 12, 2016
- Implement File Info · 0ee659e8
  jackkoenig authored May 11, 2016
  
  0ee659e8
- Remove trait StanzaPass and related dead code · 6d72dfbb
  jackkoenig authored May 11, 2016
  
  6d72dfbb
May 11, 2016
- Add test suite for Constant Propagation · a73efa2f
  Adam Izraelevitz authored Apr 27, 2016
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Add unit tests for splitting expressions and padding widths
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  a73efa2f
- Remove old SplitExp pass (replaced by SplitExpressions) · 7f9814eb
  jackkoenig authored May 10, 2016
  
  7f9814eb
- Modified Verilog compiler to use new passes · e08c8c0b
  Adam Izraelevitz authored Apr 27, 2016
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RemoveValidIf, SplitExpressions, and PadWidths
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  e08c8c0b
- Added RemoveValidIf pass. · 5fe29442
  Adam Izraelevitz authored Apr 27, 2016
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This is to start moving stuff out of Emitter and into separate passes
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  5fe29442
- Added new (and correct) Split Expressions pass · e78b2b27
  Adam Izraelevitz authored Apr 27, 2016
  
  e78b2b27
- Added pad widths to eliminate all implicit width extending · 4e784786
  Adam Izraelevitz authored Apr 27, 2016
  
  4e784786
- Added constant propagation rule for greater/less thans · 72e6e928
  Adam Izraelevitz authored Apr 27, 2016
  
  72e6e928
- Fixed emission of memory ports to all be in the same always @ clock. · c81a1dba
  Adam Izraelevitz authored Apr 27, 2016
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Changed initialization to assign the correct number of random bits.
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  c81a1dba
May 04, 2016
- Remove line in Verilog Emitter erroneously printing ); before module def · d3085ef9
  jackkoenig authored Apr 21, 2016
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Fixes #133
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  d3085ef9
- Add Tests for Check Initialization · 3d4d52ef
  Adam Izraelevitz authored Apr 27, 2016
  
  3d4d52ef
- Refactor Check Initialization to trace voids through temporary nodes · b0ce2fa1
  jackkoenig authored Apr 28, 2016
  
  b0ce2fa1
- Make style and spacing of Check Initialization more idiomatic Scala · c32b1d4a
  jackkoenig authored Apr 28, 2016
  
  c32b1d4a
- Move Check Initialization to its own file · b6075279
  jackkoenig authored Apr 28, 2016
  
  b6075279
- Add Expand Whens test · 72763a13
  jackkoenig authored Apr 28, 2016
  
  72763a13
- Rewrite ExpandWhens to memoize complex default values · 41e0f6da
  jackkoenig authored Apr 26, 2016
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Fixes #113 and Fixes #150
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  41e0f6da
- Change style and spacing of Expand Whens to be more idiomatic Scala · a5526c17
  jackkoenig authored Apr 21, 2016
  
  a5526c17
- Move ExpandWhens to its own file · 75cbdf76
  jackkoenig authored Apr 21, 2016
  
  75cbdf76
- Add Utils function getDeclaration · d2496f27
  jackkoenig authored Apr 26, 2016
  
  d2496f27
- Make simulations that time out fail when run in firrtlTests · 000a8184
  jackkoenig authored Apr 26, 2016
  
  000a8184
- Move splitRef and mergeRef from LowerTypes to Utils · e7195a2e
  jackkoenig authored Apr 26, 2016
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Make EmptyExpression part of WIR
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  e7195a2e
- Add HasInfo trait to IR, IsDeclaration mixes in HasInfo · d9303f71
  jackkoenig authored Apr 26, 2016
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Change Field from IsDeclaration to HasName

Make WDefInstance an IsDeclaration
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  d9303f71
Apr 30, 2016
- Change PassUtils to use Utils.time function · 4d6f653e
  jackkoenig authored Apr 29, 2016
  
  4d6f653e
- Cleanup Parser comments and imports - No functional changes · 4f874780
  jackkoenig authored Apr 29, 2016
  
  4f874780
- Add timing to Parser · 3251e3e2
  jackkoenig authored Apr 29, 2016
  
  3251e3e2
- Add time function to Utils · 8e99f164
  jackkoenig authored Apr 29, 2016
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time uses LazyLogging, also delete import PrimOps._ (cyclic reference)
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  8e99f164
Apr 27, 2016
- Test that nested expressions don't make it to the Emitter · 54184c2a
  Andrew Waterman authored Apr 22, 2016
  
  54184c2a
- Make sure nested expressions don't make it to the Emitter · e3a650cb
  Andrew Waterman authored Apr 22, 2016
  
  e3a650cb
- Split ValidIf from within PrimOps · 31252cd9
  Andrew Waterman authored Apr 22, 2016
  
  31252cd9
- Fixed the check for bundle equality to allow relative flips to be wrong, but... · a45c1319
  Adam Izraelevitz authored Apr 19, 2016
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Fixed the check for bundle equality to allow relative flips to be wrong, but the leaf directions are the same
```
  a45c1319