Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Update NoCircuitDedupAnnotation so it's available from firrtl.stage.FirrtlMain

Stage/Phase

Abstracts away option writing such that users no longer have to
understand scopt semantics. This adds a ShellOption class and a
HasShellOptions trait for something which provides one or more
ShellOptions. This refactors the FIRRTL codebase to use this style of
option specification.

Adds and uses DeletedWrapper to automatically generate
DeletedAnnotations.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

This switches the OptionsView/Viewer typeclass to use more canonical
approaches and helper methods. This uses a context bound instead of an
explicitly specified implicit argument. Additionally, this adds an
apply method to OptionsView to enable more canonical use of the
OptionsView typeclass.

With this, you can now do things like `Viewer[FirrtlOptions].view` in
addition to the old (and still available)
`Viewer.view[FirrtlOptions]`. Uses of the latter are updated to use
the former.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

- Add tests for DriverCompatibility.AddImplicitEmitter
- Add tests for DriverCompatibility.AddImplicitOutputFile
- Use a different top name in DriverSpec emit circuit tests for better
  coverage
- Add tests for DriverCompatibility.WriteEmitted
- Add catchWrites firrtlTests utility to intercept file writes
- Add tests for WriteOutputAnnotations
- Add tests for --custom-transforms reversing

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

This adds FirrtlStage, a reimplementation of the original FIRRTL
Driver as a Stage. This updates the original firrtl.options package to
implement FirrtlStage (namely, TransformLike is added) along with
FirrtlMain. Finally, the original FIRRTL Driver is converted to a
compatibility wrapper around FirrtlStage.

For background, Stage and Phase form the basis of the Chisel/FIRRTL
Hardware Compiler Framework (HCF). A Phase is a class that performs a
mathematical transformation on an AnnotationSeq (in effect, a
generalization of a FIRRTL transform). Curtly, a Stage is a Phase that
also provides a user interface for generating annotations. By their
construction, Phases are designed to be composed sequentially into a
transformation pipeline.

This modifies the existing options package (which provides
Stage/Phase) to build out a type hierarchy around Stage/Phase. This
adds TransformLike[A] which implements a mathematical transformation
over some type A. Additionally...

This changes the base Shell to print information about all registered
libraries/transforms. This addresses an @azidar comment about difficulty
debugging whether registration worked.

This also changes the "FIRRTL Transform Options" help text for registered
transforms to only print if registered transforms exist.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

If 'import FIRRTLParser._'  globally, 'FIRRTLParser.' is unnecessary.

Use getWidth function if it is suitable.

* Improve memoization for register const prop

DCE printf and stop statements with constant-0 enables

* Convert the RemoveAccesses object into a class.
Prevent simultaneous access to common resources when tests are run in parallel.

* Respond to comments - use object factory to preserve existing API.

This gets rid of about 10% of the generated Verilog in the rocket-chip
default config.

Designs with no SeqMems should produce empty MemConf strings, and this should be parsable without excepting (#1060)

* Add serialization support for LoadMemoryFileType in LoadMemoryAnnotation
Add custom LoadMemoryFileTypeSerializer.
Add test to verify LoadMemoryAnnotation can be correctly serialized/deserialized.

* Simplify and focus LoadMemoryAnnotation serialization/deserialization.
Respond to comments on earlier implementations.

* Add type FileType definition for current chisel3 code.

* Copy MemConf.scala from ucb-bar/barstools#35 into memlib.
This provides a data structure wrapper around the existing memory conf format
which contains both reading and writing methods, making it easier to write code
that needs to read the format.

* Add MemConf tests and use a Map[MemPort, Int] for port lists instead of a Seq[MemPort] which is a bit less fragile.

* Don't create nodes to hold Muxes with >0 void cases

* Added test case demonstrating void error

* Memoize intermediate expression when checking for WVoid-ness

* Add --nodedup option to facilitate FIRRTL to verilog regression testing.

* Short-circuit the DedupModules transform if NoCircuitDedupAnnotation exists.

* Create a simple generic graphviz renderer for DiGraph
There are three basic kinds
- A simple default renderer
- A ranked renderer that places nodes in columns based on depth from sources
- A sub-graph render for graphs that contain a loop
  - Renders just nodes that are part of first loop found
  - Plus the neighbors of the loop
  - Loop edges are shown in red.

* Create a simple generic graphviz renderer for DiGraph
- Moved the graph loop finder into DiGraph
- Fixed scala doc per Edward's comments

* Run CheckHighForm after all non-emitter transforms in firrtl tests

* Remove shlw from checks.scala

* Removed mistake in fix

* Fix FirrtlSpec fix

Fix almost all scaladoc warnings, add source links

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

This fixes all Scaladoc warnings except for those trying to link to
Java.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

* refactor InferWidths to allow for extra contraints, add InferWidthsWithAnnos

* add test cases

* add ResolvedAnnotationPaths trait to InferWidthsWithAnnos

* remove println

* cleanup tests

* remove extraneous constraints

* use foreachStmt instead of mapStmt

* remove support for aggregates

* fold InferWidthsWithAnnos into InferWidths

* throw exception if ref not found, check for annos before AST walk

Instead, just forward the exception

Previously would require all requested reviewers must have approved a PR before merging.