Have fewer ifdefs and declare the regs in the initial block

Makes Verilog more readable to both humans and scripts

We were recursing on Types of Expressions which not only is super inefficient
(especially since we are already calling InferTypes afterward), but also
duplicates each of the Type objects that need changing.

Scopt 3.5.0 adds (subjectively) sane two-column output of option
parsing help text which it enables by default.

* Upgrade Logging facility
Make thread-safe
Make logging by package name work
Use caching of class names to level for performance
Make some tests to show this working

* quick fix for dynamic logging variable

* A number of changes based on Adam's suggestions
Default LoggerState
But there is an invoke method now to handle threading issues.  This should be propagated to other
projects Driver.execute methods

* Add built-in support for string capture of Logging

* Usability fixes for logging stuff.  Settings made to the logger prior to execute/invoke will be passed along if possible.

* A couple style fixes
Comment and privatize Logger state

* Name and save string buffers used for logging

* Fix default logging state setting
Fix logging test, did not have change to command argument

* comment out logging in InlineInstanceTests

* Changed invoke to makeScope
Nested makeScopes share same state object
Removed earlier named string buffer implementation

* Better name for captor get data

* Add trace tests to make sure it works too

* Fix call into logger settings

Fixes #589

* Bugfix: pad is max(width,const) during constprop

* Fixed max syntax

Performs DCE by constructing a global dependency graph starting with top-level
outputs, external module ports, and simulation constructs as circuit sinks.
External modules can optionally be eligible for DCE via the
OptimizableExtModuleAnnotation.

Dead code is eliminated across module boundaries. Wires, ports, registers, and
memories are all eligible for removal. Components marked with a
DontTouchAnnotation will be treated as a circuit sink and thus anything that
drives such a marked component will NOT be removed.

This transform preserves deduplication. All instances of a given DefModule are
treated as the same individual module. Thus, while certain instances may have
dead code due to the circumstances of their instantiation in their parent
module, they will still not be removed. To remove such modules, use the
NoDedupAnnotation to prevent deduplication.

Now you should be able to copy paste the example code :)

* Added pass name to debug logger

* Addresses #459. Rewords transform annotations API.

Now, any annotation not propagated by a transform is considered deleted.
A new DeletedAnnotation is added in place of it.

* Added more stylized debugging style

* WIP: make pass transform

* WIP: All tests pass, need to pull master

* Cleaned up PR

* Added rename updates to all core transforms

* Added more rename tests, and bugfixes

* Renaming tracks non-leaf subfields

E.g. given:
wire x: {a: UInt<1>, b: UInt<1>[2]}

Annotating x.b will eventually annotate x_b_0 and x_b_1

* Bugfix instance rename lowering broken

* Address review comments

* Remove check for seqTransform, UnknownForm too restrictive check

Remove infix notation on calls with side effects.

Test for #468

Fixes #409 

Jar resources (unlike classes) are typically not scoped. This can create collisions if we have similarly named resources in multiple jars, especially when merging multiple projects in an IDE. Give this resource a distinct name to avoid colliding with chisel3 top.cpp.

This means CSE need only be run once to get same QOR and prevents
pathological cases. Fixes #448

Fixes bug where arbitrary expressions, if called with .expr, return the
same expression.

Also add GlobalCircuitAnnotation for creating similar annotations

Now remove DefNodes of zero width
Don't deeply walk nodes (was the source of the bug)

Use newer rocket regression spec without comb loop