Address #297

* Spec features added: AnalogType and Attach

AnalogType(width: Width):
  - Concrete syntax:
      wire x: AnalogType<10>
  - New groundtype, very restricted in use cases.
  - Can only declare ports and wires with Analog type
  - Analog types are never equivalent, thus if x and y have Analog
    types: x <= y is never legal.

Attach(info: Info, source: Expression, exprs: Seq[Expression]):
  - Concrete syntax:
      attach x to (y, z)
  - New statement
  - Source can be any groundtyped expression (UInt, SInt, Analog, Clock)
  - Exprs must have an Analog type reference an instance port
  - Source and exprs must have identical widths

Included WDefInstanceConnector to enable emission of Verilog inout
Should be mostly feature complete.
Need to update spec if PR gets accepted.

* Fixed bug where invalidated ports aren't handled

* Bugfix for VerilogPrep

Intermediate wires for invalidated instance ports were not invalidated

* Bugfix: calling create_exp with name/tpe

Returns unknown gender, which was passing through
Caused temporary wire to not be declared
Because Verilog is dumb, undeclared wires are assumed to be 1bit signals

* Addressed donggyukim's style comments

* Reworked pass to only allow analog types in attach

Restrict source to be only wire or port kind
Much simpler implementation, almost identical functionality
Clearer semantics (i think?)

* Fixup bugs from pulling in new changes from master

* comments for type eqs and small style fixes

Mem latency pipes

discussed with @azidar

Style cleanup take 3

example 1 s"${x}"
example 2 case blah => { ??? }

if methods has parens, then referencing without parens
is a method value, you don't need following underscore

missing declarations in scala doc

Fixes #308 
Fixes #193 

Style Fixes for Memory Passes

* fill empty module body with "begin end"

apparently vivado treats an empty module as a black box and triggers an error

* Changed empty module to use always @(*) begin end

Despite the fact that LinkedHashMaps preserve insertion order in traversal, it
appears that .keys and .keySet return Sets that do not provide the same
guarantee

Style Fixes for Compiler, LoweringCompiler, WIR