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- Jul 28, 2021
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Jiuyang Liu authored
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Jiuyang Liu authored
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- Jul 27, 2021
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Jiuyang Liu authored
* deprecate DependencyAPIMigration.
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Kevin Laeufer authored
This will allow chiseltest to save the hash code to disk for the purpose of caching simulation binaries.
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Jiuyang Liu authored
Add typedef in DependencyManager.
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- Jul 25, 2021
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Jiuyang Liu authored
This is a bug fix, before this PR, Scala compiler will infer `Nothing`, which makes code below failed to compile: ``` class UserCompiler extends TransformManager(Seq(Dependency(UserPass))) { override def optionalPrerequisiteOf: Seq[TransformDependency] = Seq( Dependency[DedupModules] ) } ```
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- Jul 15, 2021
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Jared Barocsi authored
* Add transform to deduplicate memory annotations * Add annotation deduplication to Dedup stage * ResolveAnnotationPaths and EliminateTargetPaths now invalidate the dedup annotations transform * Verilog emitter now throws exception when memory annotations fail to dedup Co-authored-by:Jack Koenig <koenig@sifive.com>
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- Jul 12, 2021
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Scala Steward authored
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- Jul 11, 2021
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sinofp authored
Co-authored-by:mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Scala Steward authored
Co-authored-by:mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Schuyler Eldridge authored
Signed-off-by:
Schuyler Eldridge <schuyler.eldridge@sifive.com> Co-authored-by:
mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Jiuyang Liu authored
Update sbt-scalafmt to 2.4.3
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- Jul 09, 2021
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Scala Steward authored
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- Jul 07, 2021
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Boyang Han authored
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Schuyler Eldridge authored
Relax spec on 0-bit mux select, use SFC behavior
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- Jun 30, 2021
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Schuyler Eldridge authored
Change the FIRRTL specification document to allow for 0-bit mux selects. The existing ZeroWidths pass will promote these to a 1-bit, 0-valued select signal (which effectively means that the mux can be optimized away to just the false path). Signed-off-by:Schuyler Eldridge <schuyler.eldridge@sifive.com>
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- Jun 26, 2021
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Felix Yan authored
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- Jun 23, 2021
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Jack Koenig authored
The pass injects pipe registers immediately after the declaration of the memory. This can be problematic if the clock for the associated memory port is defined after the declaration of the memory. For any memory port clocks that are driven by non-ports, we now inject a wire before the pipe register declarations to be sure there are no use-before-declaration issues.
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- Jun 22, 2021
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Albert Magyar authored
* Fixes #2206
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- Jun 19, 2021
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Jared Barocsi authored
* Restore parsed MultiInfo structure in firrtl parser * Change erroneous expected output in InfoSpec test FileInfo compression sorts the outputted entries alphabetically, but this test did not reflect that fact * Fix typo in comment * Add unit tests for file locator parsing * Fix syntax issues and typos * More redundant braces removed Co-authored-by:mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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- Jun 18, 2021
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Kevin Laeufer authored
* smt: include firrtl statement names in SMT and btor2 output * smt: remove println * smt: make tests run again and fix stale ones Apparently `private` classes aren't found by th sbt test runner.
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- Jun 17, 2021
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Schuyler Eldridge authored
Add a new option to the FIRRTL compiler, "--start-from = <form>". If used, this will cause the compiler to assume that the input FIRRTL circuit is already in the specific form. It will then skip unnecessary passes given this information. E.g., if a user requests to run "firrtl -X verilog --start-from low" then the compiler will only run transforms necessary to get from low FIRRTL to Verilog. Transforms necessary for ingesting FIRRTL IR will be run if needed (checks and type/kind/flow resolution). To implement this, a CurrentFirrtlStateAnnotation is added. Advanced users can use this directly to tell the FIRRTL compiler exactly what transforms have already been run, including the ability to ignore checks or type/kind/flow resolution if they so desire. Signed-off-by:Schuyler Eldridge <schuyler.eldridge@sifive.com>
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Schuyler Eldridge authored
* Add Protocol Buffer emission export This adds infrastructure and annotations that let a user emit a FIRRTL circuit as a Protocol Buffer. Fixes #1696. Signed-off-by:Schuyler Eldridge <schuyler.eldridge@sifive.com> * fixup! Add Protocol Buffer emission export
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- Jun 16, 2021
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Kevin Laeufer authored
* make PresetRegAnnotation public this annotation is useful outside the firrtl compiler: - to implement a pass that creates registers which need to be initialized at the beginning of simulation (e.g., for formal verification) - to support preset registers in treadle * add PresetRegAnnotation test and deal with annotation correctly in RemoveReset pass
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- Jun 15, 2021
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Schuyler Eldridge authored
Add a compiler/emitter that can target minimal high form. This will produce output that only has CHIRRTL constructs removed. Signed-off-by:Schuyler Eldridge <schuyler.eldridge@sifive.com>
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- Jun 09, 2021
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Jiuyang Liu authored
Remove java.io in MustDedup
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- Jun 08, 2021
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sinofp authored
Requested by reviewer.
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sinofp authored
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Jiuyang Liu authored
Remove java.io in FileUtils
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- Jun 06, 2021
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Jiuyang Liu authored
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Jiuyang Liu authored
Update os-lib to 0.7.8
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- Jun 05, 2021
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mergify[bot] authored
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sinofp authored
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- Jun 04, 2021
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Scala Steward authored
Co-authored-by:Jiuyang Liu <liu@jiuyang.me>
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Jiuyang Liu authored
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Jiuyang Liu authored
Update sbt-scalafix to 0.9.29
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Scala Steward authored
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Scala Steward authored
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sinofp authored
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Albert Chen authored
* ReplaceMemMacros: add target rename test case * ReplaceMemMacros: rename references to instances * fix renaming for deduped mems * use grouped DummyAnnos to preserve order * Apply suggestions from code review Co-authored-by:
Jack Koenig <koenig@sifive.com> * run scalafmt * flatten targets Co-authored-by:
Jack Koenig <koenig@sifive.com>
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