Directly subclassing Iterable is lazy-ish, but if you call any operation
on the resulting value (eg. map or ++) it will evaluate the Iterable and
return a List.

(cherry picked from commit 57b8a395

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

Transformation of mem readwriters whose address contain references to
readwriters of mems declared before it would contain invalid references
to untransformed memory readwriter, as the connection is not transformed.
This commit fixes this issue.

(cherry picked from commit 94d425f0

)

Co-authored-by: Alan L <gh@symb.olic.link>

This will make it easier to compile circuits with
older compiler versions.

(cherry picked from commit 84a7db57

)

Co-authored-by: Kevin Laeufer <laeufer@cs.berkeley.edu>

* [smem] fix read-under-write serialization

Also adds some tests for the parser and
the serializer.

* Serializer: always serialize smem ruw behavior

* test: simplify smem test circuit

(cherry picked from commit 82af22f3

)

Co-authored-by: Kevin Laeufer <laeufer@cs.berkeley.edu>

Based on https://github.com/chipsalliance/chisel3/pull/2901.

(cherry picked from commit 59f62d82

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

* allow for zero-width integer literals
* CheckWidths: ensure that width is non-negative

(cherry picked from commit 135739f0

)

Co-authored-by: Kevin Laeufer <laeufer@cs.berkeley.edu>

* Enhance find_heap_bound to not go smaller than min_step

Previously, it could accidentally get a step size smaller than the
min_step and just continue looping forever. Now the while loop has a new
termination condition to catch this case.

* Add context to find_heap_bound

This new option allows for checking additional heap sizes in increments
of the min_step above the found minimum heap size.

(cherry picked from commit 64ac2d2c

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

(cherry picked from commit b645e416

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

Also get rid of whitespace-only lines that were emitted after every when
block.

(cherry picked from commit 79c17c84

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

This is needed for emitting modules that serialize to Strings larger
than 2 GiB (the maximum String size on the JVM). It includes
micro-optimized logic for turning arbitrarily nested when scopes into
Iterable[String].

(cherry picked from commit c8745fca

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

Ever since introducing the Listener, the firrtl Parser now can hit
errors in the code converting from concrete syntax to abstract syntax
that may be due to syntax errors. These errors are essentially broken
assumptions about the structure of the parsed code because there is an
error. These errors are reported before the standard ANTLR syntax errors
are aggregated and reported, and thus could result in less than elegant
error messages (eg. NullPointerException). Now, the Parser will mask off
such errors in the event of standard syntax errors caught by the
ANTLR-generated parser.

This commit also cleans up some ParserSpec tests slightly to make the
ScalaTest style more canonical.

(cherry picked from commit 6cf4a175

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

(cherry picked from commit 50a1230d

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

* FIRRTL version support (#2543)

* Parse version and hardcode emitted version

* Throw error if version is too high

* Parse version even if rest is invalid

* Change pattern match to if statement

* Improve version grammar

* Update tests

* Remove outdated comment

* Simplify grammar and use version class

* Simplify and add no version test

* Fix for conflicting lexer rule

(cherry picked from commit 19fe90bb

)

* Waive binary compatibility breakages and bump previous artifact

Co-authored-by: Zachary Yedidia <zyedidia@gmail.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>

(cherry picked from commit a6851b8e

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

* Fix Yosys link
* Update SBT version

(cherry picked from commit c7403e80

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

Fixes #2516

Previously,

reg r : UInt<8>, clock with :
  reset => (p, UInt<8>(3))
r is invalid

would compile to:

reg r : UInt<8>, clock
r <= UInt<8>(0)

now it compiles to:

reg r : UInt<8>, clock
wire r_1 : UInt<8>
r_1 is invalid
r <= mux(reset, UInt<8>(3), r_1)

This is consistent with the behavior for a reset with an asynchronous
reset.

(cherry picked from commit 5093da03

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

(cherry picked from commit 06ccf51a

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

Problem: MemConf serialization of MemPorts was not deterministic
and the ordering seems to have changed as we move projects to 2.13
Downstream project can be adversely affected by changes in ordering
This changes specifies as specific ordering that should be compatible with
the historical one.

(cherry picked from commit f7b4aa8a

)

Co-authored-by: Chick Markley <chick.markley@sifive.com>

It is unclear if having more than one circuit annotation even works. If
it does, it is implausible that they would have the same circuit name
since that would correspond to a namespace collision.

(cherry picked from commit aea60aa1

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

Update `findTypeHints` to allow for the "class" field in JSON objects to
appear anywhere in the object. This used to rely on the field being the
very first in the object, which is easily violated when reading JSON
data generated externally, since an object's order of fields is
unspecified and can be arbitrarily scrambled.

Fixes #2497.

(cherry picked from commit a2d48a58

)

Co-authored-by: Fabian Schuiki <fabian@schuiki.ch>

Before it would just download another copy of the PDF every time I wanted to go visit the spec repo.

(cherry picked from commit 8d2262c0

)

Co-authored-by: Megan Wachs <megan@sifive.com>

This fixes handling of signed modulus and removes some redundant work.

(cherry picked from commit 95cae3cd

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

- Fix & test MemorySynthInit behavior with MemoryArrayInitAnnotation and MemoryScalarInitAnnotation.
Add test case for MemoryRandomInitAnnotation which is, on the contrary, expected not to leak any randomization statement in synthesis context.

- Refactor MemoryInitSpec for improved results readability

Context:

PR #2166 (commit: 4530152) introduced MemorySynthInit annotation to control whether statement generated with Memory*InitAnnotation (emitted within initial begin block in verilog) should be guarded with ifndef SYNTHESIS or not.
Unfortunately only one configuration (MemoryFileInlineAnnotation) has been tested while the others have been generating incorrect verilog statements (MemoryArrayInitAnnotation and MemoryScalarInitAnnotation).

Signed-off-by: Jean Bruant <jean.bruant@ovhcloud.com>
(cherry picked from commit 475c165c

)

Co-authored-by: John's Brew <46595442+johnsbrew@users.noreply.github.com>

emission-options flags swapped to match their functionality

(cherry picked from commit 922f58c8

)

Co-authored-by: Andrea Nardi <buongiorno19972@gmail.com>

Verification statements are guarded by reset.
If this reset happens to be a "preset" type
reset, they should always be active.
The easiest way to achieve that is to replace
all uses of "preset" resets with zero.

(cherry picked from commit c98ee338

)

Co-authored-by: Kevin Laeufer <laeufer@cs.berkeley.edu>

This fixes an off by one error, where 3 was erroneously
accepted as in-bounds for a memory of depth=3

(cherry picked from commit 5569c72c

)

Co-authored-by: Kevin Laeufer <laeufer@cs.berkeley.edu>

* Add FileInfo to asyncResetAlwaysBlocks

Always blocks need three FileInfo (if, true, false) to show line numbers,
but initially, every always blocks only have one FileInfo (false).

RemoveReset adds the extra two FileInfo to sync always blocks,
so sync always blocks can have line numbers.

Async always blocks don't provide their only FileInfo, so there are no line numbers.

This commit gives async always block the extra FileInfo to show line numbers for them.

This code:

```scala
import chisel3._
import chisel3.stage._
import firrtl.CustomDefaultRegisterEmission

class Test extends Module with RequireAsyncReset {
  val io = IO(new Bundle {
    val in = Input(Bool())
    val out = Output(Bool())
  })
  val valid = RegInit(false.B)
  valid := io.in
  io.out := valid
}

object Test extends App {
  new ChiselStage().execute(Array(), Seq(
    ChiselGeneratorAnnotation(() => new Test()),
    CustomDefaultRegisterEmission(useInitAsPreset = false, disableRandomization = true)
  ))
}
```

will generate this Verilog:

```verilog
module Test(
  input   clock,
  input   reset,
  input   io_in,
  output  io_out
);
  reg  valid; // @[Playground.scala 10:22]
  assign io_out = valid; // @[Playground.scala 12:10]
  always @(posedge clock or posedge reset) begin
    if (reset) begin // @[Playground.scala 10:22]
      valid <= 1'h0; // @[Playground.scala 10:22]
    end else begin
      valid <= io_in; // @[Playground.scala 11:9]
    end
  end
endmodule
```

they have correct line numbers (10, 10, 11).

* Add test for async always block line numbers

* Add comment for review

* Fix unreachable code warning by changing match order

Simulation Statements did not previously extend IsDeclaration, but now
they do so their match blocks need to be above IsDeclaration.

* Handle MemoryNoInit case in RtlilEmitter

* Remove use of deprecated logToFile

* Fix uses of LegalizeClocksTransform

Replaced all uses of LegalizeClocksTransform with
LegalizeClocksAndAsyncResetsTransform.

* Remove use of CircuitForm in ZeroWidth

Fix bugs related to arithmetic ops inlined into a mux leg.  Add formal
equivalence checks to lock in this behavior.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

This should fix issue #2436

* Add renamemap.MutableRenameMap which includes these methods without
  deprecation
* Deprecate Stringly typed RenameMap APIs which were accidentally
  undeprecated a while ago

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

* Change AnnotationSeq underlying from List to Seq

It was nothing but pointless copying.

* Make propagateAnnotations faster

There was lots of expensive logic for very little benefit.

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>