Make ExpandWhens implicitly invalidate submodule inputs (in 1.0.x) (was 712)

This is a modified form of #706 to preserve the
bugfix but preserve the [buggy] 1.0.x API that firrtl was not properly
enforcing initialization requirements for submodule inputs

The problem with #706 is that because Firrtl wasn't properly enforcing initialization requirements on submodules, code that used to work no longer does. This alternative version still fixes the incorrect Verilog generation bug but does not enforce the initialization requirement.