Add Some Missing Invalidations (bp #1541) (#1555)

* Add missing invalidations to some transforms (#1541)

This adds missing invalidations to four transforms:

  - RemoveAccesses
  - VerilogMemDelays

This necessarily updates test cases which expect exact transform
orders to reflect the new order.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

* Remove trailing comma (breaking 2.11 builds)

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-authored-by: Jim Lawson <ucbjrl@berkeley.edu>