Allow the #delay before random initialization to be overridden

The default of 0.002 can be less than the Verilog time precision, which
effectively causes it to be rounded down to 0.  So, allow the user to
`define RANDOMIZE_DELAY to some other value.

If the macro is not defined, the old behavior is preserved.

(cherry picked from commit 25a7ca97)

# Conflicts:
#	src/main/scala/firrtl/Emitter.scala