Fix VerilogModulusCleanup bug for SInt Remainder

Cast the result of the bitslice that VerilogModulusCleanup produces to
an SInt if the original remainder op was on SInts. This avoids a bug
where a remainder on SInts would be silently converted back to a UInt
and produce invalid FIRRTL if the user of the remainder required an
SInt (e.g., a mux op).

Add a test that the asSInt prim op is generated.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>