Fix invalid references generated by VerilogMemDelays (#2588) (#2600)

Transformation of mem readwriters whose address contain references to
readwriters of mems declared before it would contain invalid references
to untransformed memory readwriter, as the connection is not transformed.
This commit fixes this issue.

(cherry picked from commit 94d425f0

)

Co-authored-by: Alan L <gh@symb.olic.link>