Uniquify memories as-if they're vectors

Modify Uniquify to also view memories are vectors for the purposes of
defining a module's namespace. Previously, memories were only treated
as modules with ports for uniquification. However, if memories are not
blackboxed via ReplSeqMems, then the Verilog emitter will emit them as
vectors. While the old behavior does not result in any naming
collisions, it means that memories emitted as vectors have different
behavior than vectors emitted as vectors. This commit unifies that
behavior so that any downstream tools can expect Verilog emitted by
the FIRRTL compiler to act as if it was all uniquified.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>