Skip to content
GitLab
Commit 89be7117 authored by Albert Magyar's avatar Albert Magyar Committed by David Biancolin
Browse files

Add SeparateWriteClocks to ensure one mem write per Verilog process 

* Address @ekiwi comments from review
* Change match cases to scalafmt-mandated lined-up style

(cherry picked from commit 872b282f)
parent 2e2d9664
Hide whitespace changes
Inline Side-by-side
Supports Markdown
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment