Fix optimization of register with reset but invalid connection (#2520)

Fixes #2516

Previously,

reg r : UInt<8>, clock with :
  reset => (p, UInt<8>(3))
r is invalid

would compile to:

reg r : UInt<8>, clock
r <= UInt<8>(0)

now it compiles to:

reg r : UInt<8>, clock
wire r_1 : UInt<8>
r_1 is invalid
r <= mux(reset, UInt<8>(3), r_1)

This is consistent with the behavior for a reset with an asynchronous
reset.

(cherry picked from commit 5093da03)

# Conflicts:
#	src/main/scala/firrtl/transforms/RemoveReset.scala
#	src/test/scala/firrtlTests/transforms/RemoveResetSpec.scala