Add LegalizeAndReductionsTransform (bp #1556) (#1559)

* Add LegalizeAndReductionsTransform

Workaround for https://github.com/verilator/verilator #2300
present in Verilator versions v4.026 - v4.032. This transform turns AND
reductions for expressions > 64-bits into an equality check with all
ones. It is included as a prerequisite for all Verilog emitters.

(cherry picked from commit 96241211

)

# Conflicts:
#	src/test/scala/firrtlTests/CustomTransformSpec.scala

* Resolve backport conflicts

* Fix brittle tests

Co-authored-by: Jack Koenig <koenig@sifive.com>