Fixing lint error: x + -1 (#1374) (#1386)

* Generates lint-clean Verilog for the case: x + -1

...where x is anything and 1 is any literal.

Master behavior:

  input x : SInt<8>
  output z : SInt<9>
  z <= add(x, SInt(-2))

generates

  assign z = $signed(x) + -8'sh2;

After this PR:

  assign z = $signed(x) - 8'sh2;

If the literal is the maximum possible literal, a special case is triggered to properly trim the resulting subtraction.

Input:

  input x : SInt<2>
  output z : SInt<3>
  z <= add(x, SInt(-2))

now generates (after this PR)

  assign z = $signed(x) - 3'sh2;

* Updated documentation

* Change ArrayBuffer to ListBuffer

* Change name to minNegValue

* Remove mutable public interfaces

Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
(cherry picked from commit ce056037

)

Co-authored-by: Adam Izraelevitz <adam.izraelevitz@sifive.com>