Fix faulty MemorySynthInit behavior (backport #2468) (#2475)

* Fix faulty MemorySynthInit behavior (#2468)

- Fix & test MemorySynthInit behavior with MemoryArrayInitAnnotation and MemoryScalarInitAnnotation.
Add test case for MemoryRandomInitAnnotation which is, on the contrary, expected not to leak any randomization statement in synthesis context.

- Refactor MemoryInitSpec for improved results readability

Context:

PR #2166 (commit: 4530152) introduced MemorySynthInit annotation to control whether statement generated with Memory*InitAnnotation (emitted within initial begin block in verilog) should be guarded with ifndef SYNTHESIS or not.
Unfortunately only one configuration (MemoryFileInlineAnnotation) has been tested while the others have been generating incorrect verilog statements (MemoryArrayInitAnnotation and MemoryScalarInitAnnotation).

Signed-off-by: Jean Bruant <jean.bruant@ovhcloud.com>
(cherry picked from commit 475c165c

)

# Conflicts:
#	src/main/scala/firrtl/backends/verilog/VerilogEmitter.scala

* Fix conflict

Co-authored-by: John's Brew <46595442+johnsbrew@users.noreply.github.com>
Co-authored-by: Jean Bruant <jean.bruant@ovhcloud.com>