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Fix 0 width signals chiselsim (backport #4100) (#4103)
* Fix 0 width signals chiselsim (#4100) (cherry picked from commit 2f9faa28) # Conflicts: # src/test/scala/chiselTests/simulator/SimulatorSpec.scala * Resolve backport conflicts --------- Co-authored-by: Raffaele Meloni <raffaele.meloni99@gmail.com> Co-authored-by: Jack Koenig <koenig@sifive.com>