Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
(cherry picked from commit 15115ea6

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

Co-authored-by: jackkoenig <8584418+jackkoenig@users.noreply.github.com>

* Add and use Mill wrapper script (#4119)

This saves developers from having to install a dependency. It also
allows us to drop an old Github Actions dependency that hasn't been
updated in 2 years. This is the standard practice for projects using
Mill on Github.

(cherry picked from commit 0f2efb52

)

# Conflicts:
#	.github/workflows/test.yml
#	CONTRIBUTING.md
#	benchmark/src/main/scala/chisel3/benchmark/Benchmark.scala

* Resolve backport conflicts

---------

Co-authored-by: Jack Koenig <koenig@sifive.com>

(cherry picked from commit 25f70bd1

)

Co-authored-by: qimingchu <cchuqiming@gmail.com>

* Bump versions of Github actions to versions using Node 20 (#4116)

Node 16 is deprecated and will eventually stop being supported.

(cherry picked from commit 99aa9f1e

)

# Conflicts:
#	.github/workflows/build-scala-cli-example.yml
#	.github/workflows/ci.yml
#	.github/workflows/install-jextract/action.yml
#	.github/workflows/scala-cli-example.yml
#	.github/workflows/test.yml

* Resolve backport conflicts

---------

Co-authored-by: Jack Koenig <koenig@sifive.com>

* Add test for FlatIO port ordering (#4113)

(cherry picked from commit c3c99793

)

# Conflicts:
#	src/test/scala/chiselTests/experimental/FlatIOSpec.scala

* Added MatchesOrOmits

* Resolve backport conflicts

---------

Co-authored-by: Megan Wachs <megan@sifive.com>
Co-authored-by: Adam Izraelevitz <azidar@gmail.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>

* Fix 0 width signals chiselsim (#4100)

(cherry picked from commit 2f9faa28

)

# Conflicts:
#	src/test/scala/chiselTests/simulator/SimulatorSpec.scala

* Resolve backport conflicts

---------

Co-authored-by: Raffaele Meloni <raffaele.meloni99@gmail.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>

* Fix widths for literal values in Bundle literals (#4082)

* Fix widths for literal values in Bundle literals

Previously, the user-specified (or unspecified minimum width) of the
literal would be used in some operations like concatenation.

* Implicitly truncate too-wide literals in Bundle literals

This is to fix a bug in concatenation without breaking things relying on
implicit truncation. This will be a warning in newer versions of Chisel.

(cherry picked from commit 3939e570

)

# Conflicts:
#	core/src/main/scala/chisel3/internal/firrtl/IR.scala
#	src/test/scala/chiselTests/ConnectableSpec.scala
#	src/test/scala/chiselTests/VecLiteralSpec.scala

* Waive false binary compatibility failure

Also move waivers from files to build.sbt.

---------

Co-authored-by: Jack Koenig <koenig@sifive.com>

* Materialize wires for .ref of Aggregate views (#4080)

Fixes muxing of Aggregate views, and fixes ProbeValues of Aggregate
views.

(cherry picked from commit 5af27e5d

)

# Conflicts:
#	src/test/scala/chiselTests/experimental/DataView.scala

* Resolve backport conflicts

---------

Co-authored-by: Jack Koenig <koenig@sifive.com>

* [SVSim] Fixed non-firing AssertProperty in SVSim  (#4087)

(cherry picked from commit d3ab477e

)

# Conflicts:
#	src/test/scala/chiselTests/LTLSpec.scala
#	svsim/src/main/scala/verilator/Backend.scala

* Resolve backport conflicts

---------

Co-authored-by: Amelia Dobis <amelia.dobis@sifive.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>

* Fix literal handling for views of empty Aggregates (#4071)

Previously, a view of an empty Record or Vec would always have a
litValue of 0.

(cherry picked from commit 11c3f51c

)

# Conflicts:
#	src/test/scala/chiselTests/experimental/DataView.scala

* Fixup backport conflicts

---------

Co-authored-by: Jack Koenig <koenig@sifive.com>

* Add support for Vec literals of empty Vecs (#4070)

Also tweak Vec.Lit code to use cloneAsSuperType rather than implementing
its own version of the same concept.

(cherry picked from commit 86082b1a

)

# Conflicts:
#	src/test/scala/chiselTests/BundleLiteralSpec.scala
#	src/test/scala/chiselTests/VecLiteralSpec.scala

* Resolve backport conflicts

---------

Co-authored-by: Jack Koenig <koenig@sifive.com>

* Fix Nested Instantiate (#4018)

* minimal reproduce Nested Instantiate bug

* expose cache and elaborated defination to inner defination

* fix up

(cherry picked from commit 02b01e8b

)

# Conflicts:
#	core/src/main/scala/chisel3/experimental/hierarchy/core/Definition.scala
#	core/src/main/scala/chisel3/experimental/hierarchy/core/Instance.scala
#	core/src/main/scala/chisel3/internal/Builder.scala
#	src/main/scala/chisel3/aop/injecting/InjectingAspect.scala
#	src/main/scala/chisel3/stage/phases/Elaborate.scala

* Resolve backport conflicts

---------

Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
Co-authored-by: Jack Koenig <koenig@sifive.com>

* [chiselsim] Better fix for CIRCT 1.66- and 1.66+ (#3893)

Change the way ChiselSim moves files to track and not move files which may
be duplicated in both the default black box filelist and in the main
CIRCT-produced filelist.  Previously, this was working because a java.nio
exception was being ignored.  However, this may have been hiding bugs
where the filelist was actually pointing at a file that did not exist.

This commit also does some heavy cleanup of the code for moving files to only
use java.nio methods as opposed to relying on doing string manipulations of
paths.  The logic is intended to be the exact same as before.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
(cherry picked from commit 61df8bbf

)

* Help Scala 2.12 type inferencing with type annotations

---------

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>

(cherry picked from commit e0daaddd

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

(cherry picked from commit 81095f0f

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

Co-authored-by: jackkoenig <jackkoenig@users.noreply.github.com>

* Remove extra bit from `SRAMInterface` address width (#3830)

(cherry picked from commit 4f1f4a77

)

# Conflicts:
#	src/test/scala/chiselTests/util/SRAMSpec.scala

* Resolve backport conflicts

---------

Co-authored-by: Deborah Soung <debs@sifive.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>

* Provide require message for negative widths (#4008)

(cherry picked from commit 751a4cf8

)

# Conflicts:
#	core/src/main/scala/chisel3/Width.scala

* Resolve backport conflicts

---------

Co-authored-by: Jack Koenig <koenig@sifive.com>

Previously, the function would infinitely recurse resulting in a stack
overflow.

(cherry picked from commit ea2d1036

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

* Add requireIsAnnotatable for better errors when annotating literals (#3968)

(cherry picked from commit 4be3b6fb

)

# Conflicts:
#	core/src/main/scala/chisel3/dontTouch.scala
#	src/test/scala/chiselTests/DontTouchSpec.scala

* Resolve backport conflicts

---------

Co-authored-by: Jack Koenig <koenig@sifive.com>

* Support literals in DataView (#3964)

(cherry picked from commit ce05462c

)

# Conflicts:
#	src/test/scala/chiselTests/experimental/DataView.scala

* Resolve backport conflicts

---------

Co-authored-by: Jack Koenig <koenig@sifive.com>

(cherry picked from commit 6dfc0470

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

---------

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>
(cherry picked from commit b9f57032

)

Co-authored-by: Michiel Van Beirendonck <michiel.vanbeirendonck@esat.kuleuven.be>

* Rename Scala CLI template to example (#3917)

This avoids name aliasing with the chisel-template repository.

---------

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
(cherry picked from commit bb3c6406

)

# Conflicts:
#	.github/workflows/build-scala-cli-example.yml
#	.github/workflows/build-scala-cli-example/action.yml
#	.github/workflows/build-scala-cli-example/chisel-example.scala
#	.github/workflows/scala-cli-template.yml
#	.github/workflows/test.yml
#	docs/src/installation.md

* Resolve backport conflicts

---------

Co-authored-by: Jack Koenig <koenig@sifive.com>

* Fix ChiselStage and Builder handling of logging (#3895)

Previously, object circt.stage.ChiselStage was ignoring the Logger.
Also, Chisel was not creating its own logger scope which could lead to
clobbering of the Console when running invoking Chisel in the same
process multiple times.

Fix various places we had to workaround this behavior and fix tests
checking --log-level debug.

(cherry picked from commit 88d147d9

)

# Conflicts:
#	core/src/main/scala/chisel3/experimental/hierarchy/core/Definition.scala
#	core/src/main/scala/chisel3/internal/Builder.scala
#	docs/src/cookbooks/cookbook.md
#	src/main/scala/chisel3/aop/injecting/InjectingAspect.scala
#	src/main/scala/chisel3/stage/phases/Elaborate.scala
#	src/main/scala/circt/stage/ChiselStage.scala
#	src/test/scala/circtTests/stage/ChiselStageSpec.scala

* Resolve backport conflicts

* Make logger annotations unserializable

Change logger annotations to mix-in the Unserializable trait so that they
will not emitted by a stage.  These annotations are not intended to be
seen by CIRCT and these should be stripped from the output FIRRTL text.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

---------

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

* Use c++14 to pass the verilator check (#3876)

(cherry picked from commit 62291553

)

# Conflicts:
#	svsim/src/main/scala/verilator/Backend.scala

* Resolve backport conflicts

---------

Co-authored-by: qimingchu <1346550347@qq.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>

* Support serializing Annotations to a Writer

Previous API serializing to a String is limited by JVM max size of 2 GiB
Strings.

* Serialize to Writer instead of String in WriteOutputAnnotations

(cherry picked from commit 736f1a72

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

Fix an incorrect assumption in ChiselSim that a 'filelist.f' will exist
that includes all modules, _including blackboxes_, in the design.  Change
this to try to also copy files from the black box filelist.  This makes
ChiselSim work with CIRCT 1.66 and earlier (which put everything in
'filelist.f') and CIRCT 1.66+ (which does not include blackboxes in
'filelist.f').

Note that this is intended as a temporary solution until FIRRTL has a rock
solid ABI that is implemented by CIRCT where all modules can be discovered
under an arbitrary public module.

See CIRCT changes here: https://github.com/llvm/circt/pull/6729



Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
(cherry picked from commit 9448d326

)

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

* [website] Update chisel-template repo link to chipsalliance (#3871)

(cherry picked from commit e513da57

)

# Conflicts:
#	build.sbt

* Resolve backport conflicts

---------

Co-authored-by: Jack Koenig <koenig@sifive.com>

(cherry picked from commit 68eb2486

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

* [svsim] Make EphemeralSimulator multi-processing friendly (#3847)

(cherry picked from commit 1ff43c93

)

# Conflicts:
#	src/main/scala/chisel3/simulator/EphemeralSimulator.scala

* Resolve backport conflicts

---------

Co-authored-by: Jack Koenig <koenig@sifive.com>

(cherry picked from commit 41dd2671

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

(cherry picked from commit 8f0196fa

)

Co-authored-by: Deborah Soung <debs@sifive.com>

* Report source locator in when scoping error messages (#3804)

(cherry picked from commit d21a6635

)

# Conflicts:
#	core/src/main/scala/chisel3/Data.scala

* resolve backport conflicts

---------

Co-authored-by: Jack Koenig <koenig@sifive.com>

* Fix Reg() to properly handle clocks as rvalues (#3775)

Previously, it was not calling .ref. It was thus not properly:
1. Checking that the clock is bound hardware
2. Checking that the clock is visible in the current scope
3. Reifying the clock if its a view

Note that RegInit() was already correctly calling .ref.

(cherry picked from commit 1c348c55

)

# Conflicts:
#	src/test/scala/chiselTests/ClockSpec.scala

* Resolve backport conflicts

* fix test

---------

Co-authored-by: Jack Koenig <koenig@sifive.com>

(cherry picked from commit b3b5ab19

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

(cherry picked from commit d8991c55

)

Co-authored-by: Megan Wachs <megan@sifive.com>