* Restore default for links, "hyperlink blue" is very harsh in dark mode
* Change color of hero banner, primary color (Cal gold) is very harsh

Revert changes to the width of static shift right.  Originally, Chisel
would return a 0-bit value.  However, this violated the FIRRTL spec which
mandated that this return a 1-bit value.  FIRRTL compilers would then
clean this up, however, if a user looks at the Chisel-determined width
they would get the wrong answer.

Commit 1634320c made Chisel align with
FIRRTL.  After additional discussion, it was decided that the best course
of action was to make FIRRTL _align with Chisel_ for UInt, but not for
SInt.  Specifically, the following behaviors are what we want to move
towards:

  1. The smallest width of a UInt shifted right is 0-bit
  2. The smallest width of an SInt shifted right is 1-bit

This will then be handled with changes to the FIRRTL spec and by FIRRTL
compilers.  In the mean time, do not introduce incorrect behavior in
Chisel and preserve things the way they were.

This reverts commit 1634320c

.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

* Delete sbt-subproject, that page is very outdated and no longer applies.
* Update ScalaDoc page to modern use.
* Update Developers index to remove sbt-subproject and add ScalaDoc.

It pains me to delete a Makefile.  However, I think this is entirely
unused.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Add a new trait, `Public`, which can be used to emit FIRRTL modules which
have the public keyword.  This is a weak form of "public modules" that we
want to support for FIRRTL 4.0.0.  This does not allow for multiple,
disjoint instance graphs to be contained in a circuit, nor does it remove
the "main module" from the circuit.  However, it provides a mechanism for
plucking modules out of a circuit later and working with them.

This is self-typed on `RawModule` to prevent mix-in to an external module.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>

Change the version of the update-circt action used when running CD from an
explicit v1.0.0 to v1.  This will cause it to grab minor features and bug
fixes.  Practically, this pulls in a bug fix related to failing to
cherry-pick the staging branch.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

* [binder] Add instance graph API for iterating HW modules
* [cd] Bump CIRCT from firtool-1.64.0 to firtool-1.65.0

Co-authored-by: Asuna <SpriteOvO@gmail.com>
Co-authored-by: chiselbot <chiselbot@users.noreply.github.com>

Implement FirtoolOptions for PanamaBinding

Bump emission to use FIRRTL 4.0.0.  Since Chisel is now emitting layer-colored
probes and the work-in-progress "enablelayer" keyword, Chisel needs to emit a
version of FIRRTL that compilers will accept.

The only change to the output (other than the stated version) is "groups" are
now changed to "layers".

Note: FIRRTL 4.0.0 is not finalized yet.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

This is an automated commit generated by the `circt/update-circt` GitHub
Action.

Co-authored-by: chiselbot <chiselbot@users.noreply.github.com>

Add a function that allows the layer to be "enabled" within the current
module scope.  This has the effect of emitting the module with the
"enablelayer <layer>" FIRRTL format.  This is not currently in the FIRRTL
spec---it is being prototyped inside CIRCT and is expected to land in the
spec soon.

This is done to allow for the use case of a Test Harness needing to enable
one or more layers (more than one layer is the union of several layers)
inside a DUT in order to drive it properly.  The specific use case is to
get access to an expensive core trace inside a microprocessor that is
hidden behind a layer.

This was originally written using an API where the layer provided a trait
that enabled the layer.  This runs afoul of Scala's restriction on
inheriting the same trait multiple times.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

This is in addition to the existing support in
Definition.apply. Sometimes it is not possible to use
Definition.apply, for example, if you plan to bore ports through the
Class being constructed. The new DynamicObject.apply method supports
this, and creates a DynamicObject from the newly elaborated Class.

Co-authored-by: Richard Xia <rxia@sifive.com>

This adds support for BoringUtils.bore to bore and connect Property
ports.

This adds an API to DataMirror to query if a Data is a Property.

Since we override litOption to always be None, we need to override
isLit to check the Binding.

Previously, it was not calling .ref. It was thus not properly:
1. Checking that the clock is bound hardware
2. Checking that the clock is visible in the current scope
3. Reifying the clock if its a view

Note that RegInit() was already correctly calling .ref.

Co-authored-by: Megan Wachs <megan@sifive.com>

- Implement a simple data structure for FirtoolOptions
- use it in panamalib
- move panamaCIRCT out from converter

curl seems to be more common and is included by default in MacOS whereas
wget is not.

Module's logic that creates the implicit clock and implicit reset within
the Module's body is now implemented in new traits that users are free
to mix in to RawModule. There are also now virtual methods implicitClock
and implicitReset that the user can override to change what clock or
reset is used.

Add OM test, support iterating fields of a OM object

Add a utility to reflect on the optional color of a layer.  This will be
used by libraries that need to know if they need to put generated logic in
a layerblock or not.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Also fix some links in the README to point to local files or at least
the main branch rather than the old master branch.