.grouped(_) returns an Iterator
.toSeq on an Iterator returns a Stream in 2.12 and a List in 2.13
This can lead to changes in order when bumping from 2.12 to 2.13 that
can be avoided by simply using an eager collection explicitly.

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Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Fixes #2470

This is a quick fix for issue #2408

* Move clones to hierarchy package

* Moved D/I sinternals to new core package

* move library hooks back to hierarchy

Loosen restrictions on clocks to enable them to be connected to
DontCare, i.e., be invalidated.

Co-authored-by: Jack Koenig <koenig@sifive.com>
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Co-authored-by: Jack Koenig <koenig@sifive.com>

* Use a single field instead of two in HasId (4-bytes per HasId)
* Set the prefix to Nil after setting ref to free up memory

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Enhance views to [sometimes] support dynamic indexing and implement FlatIO

This is implemented by including any corresponding Aggregates from the
DataView.mapping in the AggregateViewBinding.childMap (which is now of
type Map[Data, Data]).

This enables dynamically indexing Vecs that are themselves elements of
larger Aggregates in views when the corresponding element of the view is
a Vec of the same type. It also increases the number of cases where a
single Target can represent part of a view.

* During sanitize, only filter the String if needed
* Do not recurse on name, saving an unnecessary call to sanitize

This reduces memory use of every HasId by 64 bytes.

Every instance of HasId (including all Data) had 2 ListBuffer vals for
recording post-naming hooks, yet this feature is almost never used.
These are now vars of type List which allows the common case of Nil to
add no incremental memory use per instance of HasId.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

This reverts commit 3c8a810e.

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Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

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Also delete an errant println in InstanceSpec

Chisel <> semantics differ somewhat from FIRRTL <= semantics,
so we only emit <= when it would be legal. Otherwise we continue
the old behavior of emitting a connection for every leaf-level
Element.

Co-authored-by: Deborah Soung <debs@sifive.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>

Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
Co-authored-by: Megan Wachs <megan@sifive.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>

* Tweaks to the Verilog-vs-Chisel Page

* Update cookbook.md

* Update verilog-vs-chisel.md

* Update verilog-vs-chisel.md

* Issue errors on out-of-range extracts when width is known

Firrtl will catch this later on, but better to error early if possible.

* Test that errors are generated on OOB extracts when width is known

Co-authored-by: Shola Ogunkelu @Shorla
Co-authored-by: Megan Wachs <megan@sifive.com>
Co-authored-by: Deborah Soung <debs@sifive.com>

Completed as part of Outreachy Internship Dec 2021-March 2022.

Widths are now padded to the maximum width of the inputs.

Co-authored-by: Jack Koenig <koenig@sifive.com>