Added Aspects to Chisel, enabling a mechanism for dependency injection to hardware modules.

Remove "-Xcheckinit" from build.sc

Require target is hardware for Vec.apply(a: UInt)

Adds a check that a Vec being indexed by a UInt is, in fact, a
hardware type. This includes a test for this.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Update website references to the new website

Avoid when(reset) construct in LFSR

Muxes and resets are only isomorphic with synchronous reset.  Use a reset
instead of a conditional to make this async-reset-safe.

Remove Deprecations since before 3.2

This renames all *FactoryBase traits to *Factory, removes
transparent *Factory objects, and propagates this flattened hierarchy
throughout the codebase.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Anything removed by this that is used by the compatibility layer is
migrated to the compatibility layer.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

This adds a clarification to the deprecation message for RawModule,
MultiIOModule, UserModule, and ImplicitModule. While these were
technically deprecated "since the beginning of time", this adds a
comment that these aliases will be removed in 3.3.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Change "since" specification from "chisel3.2" to "3.2". This aligns
with usages in the rest of the codebase.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Improve compatibility mode testing

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Fixup and enable Dummy CompatibilitySpec test

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Core deprecation "since" should be "3.2" not "3.3"

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Fix Num.+ Scaladoc

Change Num.+ Scaladoc to state that this is not a growing
addition. Note that this is problematic either way as this macro is
resolved to an abstract method. Classes implementing this typeclass
are technically free to violate what we put in the Scaladoc here.

h/t @kammoh

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Short-term patch to enable this useful behavior. In the future, we may want to rearchitect the type system and/or rethink the more edge-case connect behavior.

* Add width utility functions to avoid incorrect usage of bare log2Ceil().

* Respond to comments:
Remove apply(Data) method.
Change name(s) to signedBitLength, unsignedBitLength.

* Respond to comments - don't be lazy.
Independently calculate the bit length to verify correct operation.

* Respond to comments - return in.bitLength - 0 (not 1) for 0

* Respond to comments - update wdith for signed 0; add explicit tests.

* Add comment expressing zero width wire assumption.

* Use Verilator 4.016
Now that ucbbar/chisel3-tools has Verilator 4.016, use that for tests.

* Update Verilator version in SETUP