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  1. Jul 20, 2019
  3. Jul 19, 2019
    • Richard Lin's avatar
      Support Analog DontCare bulk-connect (#1056) · aaf963f9
      Richard Lin authored 
      Short-term patch to enable this useful behavior. In the future, we may want to rearchitect the type system and/or rethink the more edge-case connect behavior.
      aaf963f9
    • Jim Lawson's avatar
      Add width utility functions to avoid incorrect usage of bare log2Ceil(). (#819) · ae784b6e
      Jim Lawson authored 
      * Add width utility functions to avoid incorrect usage of bare log2Ceil().

* Respond to comments:
Remove apply(Data) method.
Change name(s) to signedBitLength, unsignedBitLength.

* Respond to comments - don't be lazy.
Independently calculate the bit length to verify correct operation.

* Respond to comments - return in.bitLength - 0 (not 1) for 0

* Respond to comments - update wdith for signed 0; add explicit tests.

* Add comment expressing zero width wire assumption.
      ae784b6e
  5. Jul 16, 2019
  7. Jun 27, 2019
    • Jim Lawson's avatar
      Use Verilator 4.016 (#1116) · ae740cad
      Jim Lawson authored 
      * Use Verilator 4.016
Now that ucbbar/chisel3-tools has Verilator 4.016, use that for tests.

* Update Verilator version in SETUP
      ae740cad
  9. Jun 25, 2019
  11. Jun 20, 2019
    • Chick Markley's avatar
      First crack at updating the readme (#1106) · c6376e7b
      Chick Markley authored 
      

* First crack at updating the readme
Goals
Include up front example
Simplify
Get users to things quicker
Move complicated details to wiki.

* headers were not working,
intellij and github don't use same render for .md files

* Fix verb agreement

* Add a fir filter diagram
Compact the fir-filter code a bit

* More compact filter

* Additional README.md updates

Signed-off-by: default avatarSchuyler Eldridge <schuyler.eldridge@ibm.com>

* Don't use chisel-lang.org, drop HCL

Signed-off-by: default avatarSchuyler Eldridge <schuyler.eldridge@ibm.com>

* Fix link to fir image, make it relative

* Proposed readme changes

* Resize picture, restyle doc bullets
      c6376e7b
  13. Jun 11, 2019
    • Adam Izraelevitz's avatar
      Added documentation to Decoupled, Conditionals, Counter (#1015) · 410f03b9
      Adam Izraelevitz authored 
      * Added documentation to Decoupled, Conditionals, Counter

* Fixed private Counter class error

* Move Counter class deprecation and re-definition into util package object.

* Revert "Move Counter class deprecation and re-definition into util package object."

This reverts commit f61bdddf7051522363e1d203fcd46b512047c87d.

* Restore the old Counter definition and address this in a separate PR.
We can move the deprecation warning and the type definition into the util package object (see f61bdddf7051522363e1d203fcd46b512047c87d), but then we fail tests using Counter with a `ScalaReflectionException` in Aggregate.scala:779 (in def cloneType) when:
`Some(mirror.reflect(this).symbol)` generates `type Counter is not a class`.

* Made @ducky64 change to Counter doc
Used to generate an inline (logic directly in the containing Module, no internal Module is created) hardware counter.
      410f03b9
  15. Jun 04, 2019
  17. May 23, 2019
  19. May 22, 2019
  21. May 21, 2019
    • Jim Lawson's avatar
      Repackagecore rebase (#1078) · 38727478
      Jim Lawson authored 
      * Move Bits, Data, and BitPat to chiselFrontend/src/main/scala/chisel3
 and deal with the subsequent fallout.

* Move Aggregate, Clock, Mem, Printf, Reg

* Move almost all chisel3.core definitions to chisel3 or chisel3.experimental

* Revive core package object to provide aliases for moved definitions.

* Cleanup package definitions; eliminate ambiguous implicits

* Move more definitions to experimental.
Extract BaseModule, DataMirror, ExtModule, IO into their own files.

* Put BitPat back in chisel3.util

* More experimental motion - avoid multiple import definitions.

* Add experimental.FixedPoint alias

* Add EnumType definition to core package.
Update deprecated messages to refer to correct object

* Move FixedPoint into the experimental package (but keep it in Bits.scala).

* Add missing implicits to core/package - compatibility

* Cleanup: update ScalaDoc references; remove unused imports

* Add Reset alias to core/package

* Use common 3.2 version in deprecation warning

* Move Binding from core to internal.

* Optimize imports.

* Repair IntelliJ's overly cleanliness.

* Move Bits, Data, and BitPat to chiselFrontend/src/main/scala/chisel3
 and deal with the subsequent fallout.

Move Aggregate, Clock, Mem, Printf, Reg

Move almost all chisel3.core definitions to chisel3 or chisel3.experimental

Revive core package object to provide aliases for moved definitions.

Cleanup package definitions; eliminate ambiguous implicits

Move more definitions to experimental.
Extract BaseModule, DataMirror, ExtModule, IO into their own files.

Add EnumType definition to core package.
Update deprecated messages to refer to correct object

Move FixedPoint into the experimental package (but keep it in Bits.scala).

Add missing implicits to core/package - compatibility

Cleanup: update ScalaDoc references; remove unused imports

Use common 3.2 version in deprecation warning

Move Binding from core to internal.

* Change == to reference equality (eq) in Data print (#1044)

* Remove @chiselName from MixedVec (#1045)

* Fix enum annotations (#936)

* Turned off strong enum annotations because they weren't working with Vec
indexes
* Add new EnumVecAnnotation for vecs of enums and vecs of bundles with
enum fields
* Changed Clock's width parameter back to a fixed constant value of 1
* Fixed enum annotations for Vecs of Bundles which contain enum elements
* Fixed usage of "when/otherwise" to use consistent style

* Add Record to type hierarchy documentation

* Undeprecate isLit (#1048)

* move doNotDedup to experimental (#1008)

* Aggregate coverage - aggregate tests but not publishing (#1040)

Discover a working combination of aggregate usage to enable coverage of subproject testing but publish a single Jar.
Use "scalastyle-test-config.xml" for scalastyle config in tests.
Enable "_" in method names and accept method names ending in "_=".
Re-sync scalastyle-test-config.xml with scalastyle-config.xml
This should finally fix #772.

* Check field referential equality in autoclonetype (#1047)

* Allow naming annotation to work outside builder context (#1051)

* Try to eliminate JVM hang due to static initialization deadlock (#1053)

* Make core.DontCare private to chisel3 (#1054)

Force clients to access 'DontCare' through the chisel3 package to ensure it's created as a chisel3 object and not a client object.

* Ignore empty aggregates elements when binding aggregate direction (#946)

Previously, including an empty aggregate in a Bundle would cause
a MixedDirectionAggregateException because it has no elements and thus
doesn't have a direction

* Add SampleElementBinding for Vec sample elements
* Add ActualDirection.Empty for bound empty aggregates

* Detect bundle aliasing (#1050)

* Implement connectFromBits in ChiselEnum (#1052)

This is necessary to use ChiselEnum in aggregates where things are
casted using .asTypeOf

* Optimize imports.

* Move Analog to experimental.

* More repackage cleanup - reduce differences with master.

* Cleanup chisel3 references.

* More chisel3 reference cleanup.

* Merge cleanup.

* Remove unused import

* Bump core deprecation to 3.3

* Move DontCare back into Data.scala inside package internal

* Re-indent experimental/internal package code

* Move code back to original files - facilitate comparison with other branches

* Some code motion, update imports, minimize master differences
Move exceptions up to chisel3 package object - they're part of the interface.

* More master diff minimization.

* Try to eliminate JVM hang due to static initialization deadlock (#1053)

* Ignore empty aggregates elements when binding aggregate direction (#946)

Previously, including an empty aggregate in a Bundle would cause
a MixedDirectionAggregateException because it has no elements and thus
doesn't have a direction

* Add SampleElementBinding for Vec sample elements
* Add ActualDirection.Empty for bound empty aggregates

* Implement connectFromBits in ChiselEnum (#1052)

This is necessary to use ChiselEnum in aggregates where things are
casted using .asTypeOf

* Move Analog to experimental.

More repackage cleanup - reduce differences with master.

Cleanup chisel3 references.

More chisel3 reference cleanup.

* Fix wrong directionality for Vec(Flipped())

Create Chisel IR Port() in a way that Converter is happy with.
Also add more extensive test suite for future-proofing.

Close #1063

* Move Bits, Data, and BitPat to chiselFrontend/src/main/scala/chisel3
 and deal with the subsequent fallout.

Move Aggregate, Clock, Mem, Printf, Reg

Move almost all chisel3.core definitions to chisel3 or chisel3.experimental

Revive core package object to provide aliases for moved definitions.

Cleanup package definitions; eliminate ambiguous implicits

Move more definitions to experimental.
Extract BaseModule, DataMirror, ExtModule, IO into their own files.

Put BitPat back in chisel3.util

More experimental motion - avoid multiple import definitions.

Add experimental.FixedPoint alias

Add EnumType definition to core package.
Update deprecated messages to refer to correct object

Move FixedPoint into the experimental package (but keep it in Bits.scala).

Add missing implicits to core/package - compatibility

Cleanup: update ScalaDoc references; remove unused imports

Add Reset alias to core/package

Use common 3.2 version in deprecation warning

Move Binding from core to internal.

Optimize imports.

Repair IntelliJ's overly cleanliness.

Move Bits, Data, and BitPat to chiselFrontend/src/main/scala/chisel3
 and deal with the subsequent fallout.

Move Aggregate, Clock, Mem, Printf, Reg

Move almost all chisel3.core definitions to chisel3 or chisel3.experimental

Revive core package object to provide aliases for moved definitions.

Cleanup package definitions; eliminate ambiguous implicits

Move more definitions to experimental.
Extract BaseModule, DataMirror, ExtModule, IO into their own files.

Add EnumType definition to core package.
Update deprecated messages to refer to correct object

Move FixedPoint into the experimental package (but keep it in Bits.scala).

Add missing implicits to core/package - compatibility

Cleanup: update ScalaDoc references; remove unused imports

Use common 3.2 version in deprecation warning

Move Binding from core to internal.

Optimize imports.

Merge cleanup.

Remove unused import

Bump core deprecation to 3.3

Move DontCare back into Data.scala inside package internal

Re-indent experimental/internal package code

Move code back to original files - facilitate comparison with other branches

Some code motion, update imports, minimize master differences
Move exceptions up to chisel3 package object - they're part of the interface.

More master diff minimization.

Fix minor discrepancies with repackagecore-testbed

* Remove redundant imports
As part of its import updating process, IntelliJ converted some import statements to `import package.{object, _}`. Is this intended to show an explicit dependency on `package.object` and a further dependency on `package` implicits? Unsure. Replace these with `import package._`

* Move the BaseModule object into the internal package.
      38727478
  23. May 14, 2019
    • Chick Markley's avatar
      RawModule with no reset should be able to use withClock method. (#1065) · 89ef4d78
      Chick Markley authored 
      * RawModule with no reset should be able to use withClock method.
- refactor ClockAndReset
  - now has `clockOpt: Option[Clock]` and `resetOpt: Option[Reset]` constructor params
  - convenience methods clock and reset tries to deref the option
  - ClockAndReset.empty is factory method for (None, None)
- In Builder
  - forcedClock does not check resetOpt now
  - forcedReset does not check clockOpt now
- withClock no longer looks at resetOpt
- withReset no longer looks at clockOpt
- Module starts with empty ClockAndReset

* RawModule with no reset should be able to use withClock method.
Refactor again based on @ducky64 comments
- refactor away ClockAndReset, now builder just has a
  - currentClock
  - currentReset
- withClock, withRest, withClockAndReset just use these fields directly

* RawModule with no reset should be able to use withClock method.
- Fixed typo in withReset handler, now picks up new reset
      89ef4d78
    • Schuyler Eldridge's avatar
      Merge pull request #1022 from freechipsproject/cleanup-scaladoc · df0e0b1c
      Schuyler Eldridge authored 
      Miscellaneous Scaladoc Cleanup
      df0e0b1c
    • Schuyler Eldridge's avatar
      Fix miscellaneous Scaladoc warnings · 86530051
      Schuyler Eldridge authored 
      

Signed-off-by: default avatarSchuyler Eldridge <schuyler.eldridge@ibm.com>
      86530051
  25. May 13, 2019
  27. May 11, 2019
  29. May 10, 2019