Elimated some inadvertant typographical differences with master

in issue93 https://github.com/ucb-bar/chisel3/issues/93

Added an empty finish method to BasicTester to be overriden in HW testers where a finish is needed, to assemble testing circuit
Changed OrderedDecoupledHWIOTester and SteppedHWIOTester to override the finish in BasicTester
TesterDriver's execute methods wraps the tester in a function that instantiates the tester then calls it's finish method and then returns the tester
Changed the unitTest files per latest changes

Update README with more architecture details and new testing flow

more fixes to router, got some new firrtl error downstream

# Conflicts:
#	src/main/scala/Chisel/util/Decoupled.scala

Fixed up various tests in response

This allows us to share Verilog test harnesses between the two.