Co-authored-by: Tynan McAuley <tynan@niobiummicrosystems.com>

This allows users to get a ClassType for use in other Property types,
which is especially useful when constructing aggregate Property types
of a specific Class.

It is shockingly annoying to get information out of ScalaTest here.

Also add Verilator instructions to install page.

---------

Co-authored-by: Megan Wachs <megan@sifive.com>
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Use tabs to show mapping for releases by default, but include
prereleases in another tab.

Change the checking logic for the legality of a probe define destination
to align with FIRRTL specification language introduced recently [1].
Specifically, this enforces the following sentence:

> An operation that "writes" to a probe must be in a region whose layer
> color is enabled when the probe's layer color is enabled.

Previously, Chisel was more restrictive and would only allow writing to a
probe whose color was the same as the layer block you are currently in.
However, as has been worked out in CIRCT and elsewhere, it is fine to
drive a probe from any region that is enabled when the probe is also
enabled.

Practically, this gets some Chisel code passing that was legal by a FIRRTL
compiler, but Chisel was refusing to generate it.

CC: @rwy7

[1]: https://github.com/chipsalliance/firrtl-spec/commit/673aa08cc31883aa90eca5ceaa6bf0017f3165fa



Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

This adds an API for integer Property shift right.

This supports format strings for assert and assume statements.
Internal representaion of `Verification` object is modified in a similar way to
`Print`. Cover cannot be used with a format string so conversion raires an exception
when we try constructing a cover statement with a format string.

This adds an API for integer Property multiplication.

This allows Properties to be used to build up expressions in terms of input Properties and literals.

* Apply some suggestions from post-merge code review
* Add "use" to CLI option: --use-legacy-shift-right-width
* Improve stability of emitted FIRRTL and Verilog when using legacy
  option
* DRY out the tests

bump nix and use scala-cli from upstream

Fix a bug where a Definition's root module would be incorrectly marked
public.  Definitions currently create a separate Circuit for each
Definition.  The logic to control marking the main module public relied on
marking the last module in the circuit public.  However, this incorrectly
assumed that there was one Circuit when, in actuality, there are
multiple.  (This commit ignores questions of whether or not it should work
this way.)

Instead, use the DyanmicContext `inDefinition` variable to execute this
code path to set the main module public when the Builder is not working
with a Definition.

Fixes #3834.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Drop an argument from the Builder.build method which is only used to
change behavior when building Definitions.  Instead, rely on the
`inDefinition` variable made available by the DynamicContext.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Change the width of static shift right

New ChiselOption UseLegacyShiftRightWidthBehavior with CLI
--legacy-shift-right-width will configure Chisel to emulate the old
Chisel and FIRRTL behavior for the width of static shift right.

This option is only intended for migrating old code and will eventually
be removed.

* A UInt shifted right by a static amount >= its width will now result
  in a 0-bit UInt
* An SInt shifted right by a static amount >= its width will now result
  in a 1-bit SInt (the sign bit)

This is a change for SInts which Chisel would treat the output as a
0-bit SInt. However, FIRRTL implemented different behavior where both
UInts and SInts would result in 1-bit values (which shifted right by an
amount >= the width of the input).

This makes the width behavior consistent with the FIRRTL 4.0.0 spec.

* [cd] Bump CIRCT from firtool-1.65.0 to firtool-1.66.0

This is an automated commit generated by the `circt/update-circt` GitHub
Action.

* Update BoringUtils test for FIRRTL 4.0 (#3816)

Fix a BoringUtils test that was checking for the name of a define produce
by CIRCT.  This was changed slightly in FIRRTL 4.0.  Align the test with
the new Verilog macro name.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Co-authored-by: chiselbot <chiselbot@users.noreply.github.com>

Add `mlirBytecodeStream` to `PanamaCIRCT`

Revert changes to the width of static shift right.  Originally, Chisel
would return a 0-bit value.  However, this violated the FIRRTL spec which
mandated that this return a 1-bit value.  FIRRTL compilers would then
clean this up, however, if a user looks at the Chisel-determined width
they would get the wrong answer.

Commit 1634320c made Chisel align with
FIRRTL.  After additional discussion, it was decided that the best course
of action was to make FIRRTL _align with Chisel_ for UInt, but not for
SInt.  Specifically, the following behaviors are what we want to move
towards:

  1. The smallest width of a UInt shifted right is 0-bit
  2. The smallest width of an SInt shifted right is 1-bit

This will then be handled with changes to the FIRRTL spec and by FIRRTL
compilers.  In the mean time, do not introduce incorrect behavior in
Chisel and preserve things the way they were.

This reverts commit 1634320c

.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

* Delete sbt-subproject, that page is very outdated and no longer applies.
* Update ScalaDoc page to modern use.
* Update Developers index to remove sbt-subproject and add ScalaDoc.

It pains me to delete a Makefile.  However, I think this is entirely
unused.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>