Flag is `-DdisableFatalWarnings`
Add flag to a number of places in build.sbt

Also check ScalaDoc generation in CI

* In BoringUtils replace deprecated SyncVar with BuilderContextCache
* Handle potential in-exhaustive match error
* Changes lines to linesIterator to fix deprecation warning
* Change build.sbt to make fatal warnings error come after suppressed warnings

Fix a bug where "--split-verilog" was not properly passed into the
CIRCTOptions struct.  Add a test to lock in the correct behavior.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Deprecate ProtoBufFileFormat and warn if a user is doing Protobuf
emission.  This will be ripped out in Chisel 5.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Remove an unnecessary "currentState" argument when constructing the
internal PhaseManager of CIRCTStage.  This is no longer necessary given
that CIRCTState doesn't have to interoperate with SFC in any way.

This enables removal of this phase on the chisel5 branch.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Remove a bunch of unnecessary code that depends on SFC features from the
AnnotatingDiamondSpec.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Add an option to "circt.stage.ChiselStage", "--split-verilog", which
replaces the janky "firrt.EmitAllModulesAnnotation" method of generating
one-file-per-module output and output file splitting in "firtool".
Leave in the old behavior as a run-time warning until this gets removed
sometime after the Chisel 5 release.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Deprecate CIRCTStage and CIRCTMain.  These are stage-based wrappers
around just running firtool that are roughly equivalent to FirrtlStage
and FirrtlMain that did this for the SFC.  These do not have users and
it is unclear why these should persist given that
circt.stage.ChiselStage subsumes almost all use cases (going Chisel to
Verilog or Chisel to CHIRRTL and then using the build system to go from
CHIRRTL to Verilog).

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Remove an unnecessary optionalPrerequisite of CIRCTStage on the SFC
Compiler phase.  This is entirely unnecessary given that there is no
longer an SFC -> MFC handoff path within CIRCT-based Chisel compilation
flows.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Deprecate this Annotation/Option which is only used by
chisel3.stage.ChiselStage.  An equivalent effect can be had with the
emitCHIRRTL method of the ChiselStage$ object or using the "--target
chirrtl" option of the ChiselStage class.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Modify tests, other than ChiselStageSpec, to all use
circt.stage.ChiselStage and not chisel3.stage.ChiselStage.  This paves
the way for the deletion of the latter in Chisel 5.

Note: there is one bug in the Trace API resulting in a commented out
test.  This is tracked with this CIRCT issue:

  - https://github.com/llvm/circt/issues/4661



Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

* Use InstanceKeyGraph instead of InstanceGraph
* Get rid of use of experimental.IO
* Symbol("s") instead of 's
* .toOption.get instead of .right.get
* No need to mix in AutoCloneType
* fromUnescaped instead of fir.StringLit
* MutableRenameMap instead of RenameMap
* Remove checkScalaVersion
* More use empty parens on method calls that need them
* getDeclaredConstructor().newInstance() not .newInstance()
* Erasure fixes
* () needed for some methods
* use object BackendUtilities
* use proper ChiselEnum
* use proper SourceInfo
* fix possible match errors
* use proper InstanceId
* use proper requireIsHardware
* processEscapes instead of treatEscapes
* use @nowarn() on things we are not able to fix in code at this time
  Add TODO comments to revisit these issues

---------

Co-authored-by: Jack Koenig <koenig@sifive.com>

Copy relevant tests about chisel3.stage.ChiselStageSpec into
circt.stage.ChiselStageSpec.  This covers cases related to exception
handling and error reporting.  All other tests are already duplicated.

This is done in preparation to remove chisel3.stage.ChiselStage on the chisel5
branch. (!!!)

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

* Fix :<>= for Wires of Flipped OpaqueTypes
* Change ConnectableSpec to use circt.stage.ChiselStage

Cause the ChiselCircuitAnnotation (which is Unserializable and will be
dropped) to be passed through the CIRCT phase.  This is necessary to
enable certain D/I use cases where an ImportDefinitionAnnotation is
constructed from a ChiselCircuitAnnotation returned from a prior
ChiselStage invocation.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Make ImportDefinitionAnnotation and DesignAnnotation pass around the
firtool call in the CIRCT phase so that these can be used by later
Chisel elaborations which may chain off of an initial ChiselStage call.
(This is a frequent pattern in D/I and is used in
SeparableElaborationSpec.)

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Make this passthrough along with DesignAnnotation.

Remove the dependency of circt.stage.ChiselStage on
chisel3.stage.ChiselStage.  Remove the internal call to ChiselStage and
instead directly construct a PhaseManager that uses the target phases of
ChiselStage directly.

Add a new argument type to the existing "--target" option of
circt.stage.ChiselStage, "chirrtl", to indicate that specification
FIRRTL (in the specification textual format and not MLIR) should be
produced.

Use this new option to migrate two methods of ChiselStage$, emitCHIRRTL
and convert, away from using a call to chisel3.stage.ChiselStage.

Add tests of the new option, emitCHIRRTL, and convert.

Simplify an existing test that erroneously fails with the new elaborate.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Builder ContextCache

Deprecated chisel3.util.experimental.group since Chisel 3.6 as this is
an API unsupported by the MFC.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Deprecate existing ChiselStage class and object as this will be removed
in Chisel 5.  Add a message telling people to switch to the equivalent
circt class/object.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

* Fixed tricky Option mod stuff in BiConnect
* Add `: Unit =`  where necessary
* Mostly fixes for getLines needing parens
* Fixed up DataMirror imports

Simplify the dependency specification for CIRCT stage/phase infra to
enable removal of some FIRRTL phases on the chisel5 branch.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

This allows users to see what name Chisel plans to give a Data. This
name is NOT guaranteed and the docs warn heavily about that.

Deprecate DataMirror alias in chisel3.experimental.

Move package object internal from RawModule.scala to
internal/package.scala.

Remove dropping of RunFirrtlTransformAnnotation.  This isn't necessary
to drop as firtool will drop these if it sees them.  There is utility in
_not_ dropping these as it removes a dependency from the "circt" package
on transforms that will be removed from the "firrtl" package on the
chisel5 branch.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Convert/enable testing of loadMemoryFromFile and
loadMemoryFromFileInline to use the MLIR-based FIRRTL Compiler (MFC).
The only change to the tests is that MFC will _not_ lower aggregate
memories.  (This is an intentional behavior that is a full realization
of the "SimplifyMems" pass in SFC, but extended to work with mask bits.)

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Re-enable BoringUtilsSpec and update it in minor ways to work with MFC.
The MLIR-based FIRRTL Compiler (MFC) now supports existing BoringUtils
APIs after:

- https://github.com/llvm/circt/commit/05ca6572e0a4962599cdb0f21cdc81dd9f4d86fb



Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Change the CIRCT phase to no longer drop the CombinationalPath
annotation.  This dropping behavior was done to enable an SFC->MFC
handoff where the SFC can produce this annotation.  Chisel can never
produce this annotation, so it is safe to have MFC error if it sees it.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

It was previously aliased from chisel3.internal which is bad for
ScalaDoc.

* Add explicit default `case` for non-exhaustive matches
Report the variable being matched
Improved messages for exceptions caught by
non-exhaustive matches

* Made an InternalErrorException to encapsulate match errors

* scalafmt

* Address review comments

* uses 2.12 adapter LazyList = Stream

Remove an incorrect code path in the CIRCT phase that would convert a
"ReplSeqMemAnnotation" into a "-blackbox" argument.  This option has
existed for a long time and this would just cause "firtool" to error.
Users will need to use the dedicated "-repl-seq-mem" options to
"firtool" going forward (which is exactly what they have to do now).

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>