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This adds an API for integer Property shift right.

This supports format strings for assert and assume statements.
Internal representaion of `Verification` object is modified in a similar way to
`Print`. Cover cannot be used with a format string so conversion raires an exception
when we try constructing a cover statement with a format string.

This adds an API for integer Property multiplication.

This allows Properties to be used to build up expressions in terms of input Properties and literals.

* Apply some suggestions from post-merge code review
* Add "use" to CLI option: --use-legacy-shift-right-width
* Improve stability of emitted FIRRTL and Verilog when using legacy
  option
* DRY out the tests

bump nix and use scala-cli from upstream

Fix a bug where a Definition's root module would be incorrectly marked
public.  Definitions currently create a separate Circuit for each
Definition.  The logic to control marking the main module public relied on
marking the last module in the circuit public.  However, this incorrectly
assumed that there was one Circuit when, in actuality, there are
multiple.  (This commit ignores questions of whether or not it should work
this way.)

Instead, use the DyanmicContext `inDefinition` variable to execute this
code path to set the main module public when the Builder is not working
with a Definition.

Fixes #3834.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Drop an argument from the Builder.build method which is only used to
change behavior when building Definitions.  Instead, rely on the
`inDefinition` variable made available by the DynamicContext.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Change the width of static shift right

New ChiselOption UseLegacyShiftRightWidthBehavior with CLI
--legacy-shift-right-width will configure Chisel to emulate the old
Chisel and FIRRTL behavior for the width of static shift right.

This option is only intended for migrating old code and will eventually
be removed.

* A UInt shifted right by a static amount >= its width will now result
  in a 0-bit UInt
* An SInt shifted right by a static amount >= its width will now result
  in a 1-bit SInt (the sign bit)

This is a change for SInts which Chisel would treat the output as a
0-bit SInt. However, FIRRTL implemented different behavior where both
UInts and SInts would result in 1-bit values (which shifted right by an
amount >= the width of the input).

This makes the width behavior consistent with the FIRRTL 4.0.0 spec.

* [cd] Bump CIRCT from firtool-1.65.0 to firtool-1.66.0

This is an automated commit generated by the `circt/update-circt` GitHub
Action.

* Update BoringUtils test for FIRRTL 4.0 (#3816)

Fix a BoringUtils test that was checking for the name of a define produce
by CIRCT.  This was changed slightly in FIRRTL 4.0.  Align the test with
the new Verilog macro name.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Co-authored-by: chiselbot <chiselbot@users.noreply.github.com>

Add `mlirBytecodeStream` to `PanamaCIRCT`

Revert changes to the width of static shift right.  Originally, Chisel
would return a 0-bit value.  However, this violated the FIRRTL spec which
mandated that this return a 1-bit value.  FIRRTL compilers would then
clean this up, however, if a user looks at the Chisel-determined width
they would get the wrong answer.

Commit 1634320c made Chisel align with
FIRRTL.  After additional discussion, it was decided that the best course
of action was to make FIRRTL _align with Chisel_ for UInt, but not for
SInt.  Specifically, the following behaviors are what we want to move
towards:

  1. The smallest width of a UInt shifted right is 0-bit
  2. The smallest width of an SInt shifted right is 1-bit

This will then be handled with changes to the FIRRTL spec and by FIRRTL
compilers.  In the mean time, do not introduce incorrect behavior in
Chisel and preserve things the way they were.

This reverts commit 1634320c

.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

* Delete sbt-subproject, that page is very outdated and no longer applies.
* Update ScalaDoc page to modern use.
* Update Developers index to remove sbt-subproject and add ScalaDoc.

It pains me to delete a Makefile.  However, I think this is entirely
unused.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Add a new trait, `Public`, which can be used to emit FIRRTL modules which
have the public keyword.  This is a weak form of "public modules" that we
want to support for FIRRTL 4.0.0.  This does not allow for multiple,
disjoint instance graphs to be contained in a circuit, nor does it remove
the "main module" from the circuit.  However, it provides a mechanism for
plucking modules out of a circuit later and working with them.

This is self-typed on `RawModule` to prevent mix-in to an external module.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>

Change the version of the update-circt action used when running CD from an
explicit v1.0.0 to v1.  This will cause it to grab minor features and bug
fixes.  Practically, this pulls in a bug fix related to failing to
cherry-pick the staging branch.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

* [binder] Add instance graph API for iterating HW modules
* [cd] Bump CIRCT from firtool-1.64.0 to firtool-1.65.0

Co-authored-by: Asuna <SpriteOvO@gmail.com>
Co-authored-by: chiselbot <chiselbot@users.noreply.github.com>

Implement FirtoolOptions for PanamaBinding

Bump emission to use FIRRTL 4.0.0.  Since Chisel is now emitting layer-colored
probes and the work-in-progress "enablelayer" keyword, Chisel needs to emit a
version of FIRRTL that compilers will accept.

The only change to the output (other than the stated version) is "groups" are
now changed to "layers".

Note: FIRRTL 4.0.0 is not finalized yet.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

This is an automated commit generated by the `circt/update-circt` GitHub
Action.

Co-authored-by: chiselbot <chiselbot@users.noreply.github.com>

Add a function that allows the layer to be "enabled" within the current
module scope.  This has the effect of emitting the module with the
"enablelayer <layer>" FIRRTL format.  This is not currently in the FIRRTL
spec---it is being prototyped inside CIRCT and is expected to land in the
spec soon.

This is done to allow for the use case of a Test Harness needing to enable
one or more layers (more than one layer is the union of several layers)
inside a DUT in order to drive it properly.  The specific use case is to
get access to an expensive core trace inside a microprocessor that is
hidden behind a layer.

This was originally written using an API where the layer provided a trait
that enabled the layer.  This runs afoul of Scala's restriction on
inheriting the same trait multiple times.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

This is in addition to the existing support in
Definition.apply. Sometimes it is not possible to use
Definition.apply, for example, if you plan to bore ports through the
Class being constructed. The new DynamicObject.apply method supports
this, and creates a DynamicObject from the newly elaborated Class.