* Update comments describing Decoupled/ReadyValid.
It seems there is a valid use case for EnqIO/DeqIO and updating the comments may clear some of the confusion and encourage their usage.

* Update comments - no functional changes.
Re-flow comments for ReadyValidIO()
Add gen param to DecoupledIO() and IrrevocableIO().

* Update code and comment now that #492 is resolved

Enables changing FIRRTL's IR to only accept multiplication of identical
types.

Fixes #495

Helps distinguish between Records/Bundles defined in Chisel._ vs.
chisel3._. Also override compilationOptions when bulk connecting
Records/Bundles defined in Chisel._. This allows Records/Bundles defined
in Chisel._ code to be correctly bulk connected in chisel3._ code.

"Test a simple interval add"

* Remove explicit import of NotStrict - fixes #492

* Provide macro for MemBase.apply().

* Provide macro for MemBase.apply().
Since a macro cannot override an abstract method, provide a concrete
apply method n VecLike() that we can override with a macro.

* Remove concrete apply() in VecLike.
Since MemBase no longer extends the trait VecLike, we do not require a concrete method to which we can apply a macro to extract the appropriate CompileOptions.

* Add missing implicit compileOptions to do_pad() and do_zext().
The latter caused:
```
[error] /vm/home/jenkins/workspace/rocket-chip_with_chisel3/hardfloat/src/main/scala/MulAddRecFN.scala:205: too many arguments for method do_zext: (implicit sourceInfo: chisel3.internal.sourceinfo.SourceInfo)chisel3.core.SInt
[error]     val CDom_sExp = io.fromPreMul.sExpSum - io.fromPreMul.doSubMags.zext
```

* Add SourceInfoTransform macros to Vec methods in order to avoid apply() chain issues.
Since utils methods are no longer NotStrict, Pipe objects need access to the client's compile options. There may be more.

* Respond to review comments.
Don't propagate SourceInfo through helper functions.
Replace old usages of CompileOptionsTransform with the now equivalent SourceInfoTransform and redefine CompileOptionsTransform to only deal with CompileOptions.
Just thread CompileOptions (not SourceInfo) through deprecated functions.

* Remove explicit import of NotStrict - fixes #492

* Provide macro for MemBase.apply().

* Provide macro for MemBase.apply().
Since a macro cannot override an abstract method, provide a concrete
apply method n VecLike() that we can override with a macro.

* Remove concrete apply() in VecLike.
Since MemBase no longer extends the trait VecLike, we do not require a concrete method to which we can apply a macro to extract the appropriate CompileOptions.

* Partially revert 8e4ddc62

It was an incomplete fix for handling Vec(0).

* Fix assignment from 0-entry Vec: add test

375e2b6a introduced a regression for bundles
containing zero-entry Vecs.  Until zero-width UInts are supported, the
zero-entry Vecs need to be flattened out before doing asUInt/asTypeOf on
a bundle.  Undoing that commit's replacement of Data.flatten with
Aggregate.getElements is the best interim fix.

Add temporary SInt variety of test to IntervalSpec to debug via symmetry
Some work on Interval literals
Some emitting fixes, based on toStrings of things like KnownIntervalRange

* still trying to find right mix

* Making some progress on Mux1H

* Mux1H that works in non-optimzed fashion for FixedPoint, works pretty well in general
Catches some additional problem edge cases
Some tests that illustrate most of this

* Moved in Angie's code for handling FixedPoint case
Cleaned up tests considerably, per @ducky64 review

* Just a bit more cleanup

Fixes #554

Using the sample_element of the created wire is incorrect because Wires have no
direction so the Wire constructed for a Vec of Module IO was constructed
incorrectly. Fixes #569 and resolves #522.

Make it relatively easy to override a single CompileOption.

Fixes #567

Creating FixedPoint literals was throwing away width

This caused one hot muxing problems in dsptools
FixedPoint spec fixed based on error uncovered by this change

This also allows asUInt/asTypeOf to work properly on those Bundles,
even though zero-width wire support is lacking.

Use fold(0) instead of reduce to handle the corner case.

Allow muxing FxP of different widths and BPs

# Conflicts:
#	chiselFrontend/src/main/scala/chisel3/core/Bits.scala