This information is known in the Record itself.

This resolves an issue where Mems with a Record data type would run into
issues during FIRRTL emission or conversion when the refs of their
elements would be accessed to name the fields of the FIRRTL type.

This problematic behavior resulted from the following behaviors:
* Refs of Record elements are only set by _onModuleClose
* _onModuleClose is only called on Records added to the _ids of a Module
* Data are only added to _ids of Module on binding

The last point is new behavior in this PR

No longer create a pointer from parent to every HasId, only do it by
default for BaseModules and MemBases. Add pointer from parent to Data
upon binding the Data.

Fixes #1606

Previously, the Data itself would be put on the prefix stack and its
full name would be used as the prefix for subsequent names. This meant
that prefixes would grow quadratically as the prefix is present both on
the Data pushed to the stack, and on the stack itself. This is fixed by
just using the "local" name of the Data being pushed on the stack.

A related issue is deferring the name resolution. This led to unintuitive
behavior when the name of a Data used as a prefix is overridden later
(usually when the Data is a return value). The overriding name would
show up in prefixes twice instead of once. It is much more intuitive to
grab the name at the moment of the connection creating the prefix rather
than deferring to later.

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

* Fix broken mdoc

* Added test-chisel-docs to ci workflow

* Add requirement on build-treadle job

* Added forgotton colon

* Forgot cd into chisel3 dir

* moved three docs into explanations

* Updated reference

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>

Change source and other relevant files to use SPDX license
LICENSE file moved from src/ to ./
Changed license file to refer to this per recommendation
using_spdx_license_list_short_identifiers

WARNING: Tests fail with as of yet undiagnosed error
```
[error] Failed: Total 691, Failed 19, Errors 0, Passed 672, Ignored 15
[error] Failed tests:
[error] 	chiselTests.QueueSpec
[error] 	examples.VendingMachineGeneratorSpec
[error] 	chiselTests.HarnessSpec
[error] 	chiselTests.ConnectSpec
[error] 	chiselTests.aop.SelectSpec
[error] 	chiselTests.PopCountSpec
[error] 	chiselTests.CloneModuleSpec
[error] (Test / test) sbt.TestsFailedException: Tests unsuccessful
[error] Total time: 379 s (06:19), completed Sep 30, 2020 12:38:17 AM
sbt:chisel3>
```

* Fix broken mdoc

* Added test-chisel-docs to ci workflow

Co-authored-by: Megan Wachs <megan@sifive.com>

Use caching to reduce number of expensive lookups

* Added documentation. Bugfix in plugin. Moved plugin APIs to separate package

* Revert reg naming behavior (omit underscore)

* Added documentation and a test

* Addressed reviewer feedback.

Test all cases in ParameterizedOneHotTesters

Co-authored-by: Jack Koenig <koenig@sifive.com>

ChiselCircuitAnnotation no longer extends CustomFileEmission, rather it
is Unserializable. Also the --chisel-output-file is added to the
ChiselCli.

New phase AddSerializationAnnotations constructs a
CircuitSerializationAnnotation from ChiselCircuitAnnotation and
ChiselOutputFileAnnotation. Both .fir and .pb file formats are
supported. Default format is .fir unless a --chisel-output-file is
specified with a .pb extension.

* fix loadMemoryFromFile to work with binary

Passed in hexOrBinary parameter to ChiselLoadMemoryAnnotation

* Added test for binary format support in loadMemoryFromFile

* Added test for binary format support in loadMemoryFromFile

Using JVM system properties sbt.sourcemode and sbt.workspace, one can now
easily build chisel3 with firrtl from source

Example use:

Assuming firrtl is cloned into the chisel3 root directory:
$ sbt -Dsbt.sourcemode=true -Dsbt.workspace=$PWD

Alternatively, one can set these properties in .sbtopts which can then
be committed, enabling building from source by default

* add chisel plugin to mill build system.

* update for review.

It shouldn't be removed until we also remove the underlying chisel3.Driver.

A quick fix for the developer's confusion

* Add ChiselPhase

* Use ChiselPhase in ChiselStage, remove targets

Switch from a one-off PhaseManager inside ChiselStage to actually
using the newly added ChiselPhase. This removes the targets
method (and API) from ChiselStage.

* Stop writing to files in ChiselStage$ methods

Change the ChiselStage companion object methods, elaborate and
convert, to not write files. Under the hood, these are switched from
using ChiselStage (which, like all phases, will write files) to using
ChiselPhase.

* Test that ChiselStage$ methods write no files

Modify existing ChiselStage object method tests to check that no files
are written.

* Expand ChiselStage$ API with more helpers

This adds additional methods to the ChiselStage object for going
directly from a Chisel module to a string including: CHIRRTL, high
FIRRTL IR, Verilog, and SystemVerilog.

Differing from their ChiselStage class counterparts, these take no
arguments other than the module and write no files.

* Add tests of new ChiselStage$ helper methods

* Use ChiselStage object in tests

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

It must run after the typer, but doesn't need to "run right after". The
stricter dependency conflicted with the semanticdb-typer.

* Updated PR template to include checklist and documentation updates

* Change milestones to 3.x.x

* updated milestones

* Added website docs and mdoc. Removed all warnings

* Updated README and added build to circle ci

* Added how to build documentation, deprecated wiki

* Fix copypasta

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Remove usages of the deprecated trait PreservesAll and use an explicit
false invalidates. Additionally, all phases are converted to be more
canonical in there specification of dependencies by:

  1. Overriding all default dependency implementations
  2. Using def instead of val

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Use inheritance to make TesterDriver Backend API extensible, then define
a TreadleBackend in the test project

Also fix BuildInfo in mill

Leverages chiselRuntimeDeprecated infrastructure. As such it is not
currently suppressible.

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

* Deprecate Module.io and BlackBox.io

This is a step toward unification of Module with MultiIOModule.
The future of BlackBox is a bit less clear, but its existing API can be
maintained without the io virtual method.

The trickier API to maintain is auto-IO wrapping for compatibility
Modules and BlackBoxes. This will probably require reflection to support
once the io virtual method is removed.

* Improve deprecation warning for io

* Fix emit{Firrtl,Verilog} for CustomFileEmission

Change ChiselStage helper methods for emitting FIRRTL (emitFirrtl) and
Verilog (emitVerilog) to look for Circuit and Verilog annotations
instead of DeletedAnnotations. This is needed after migrating to the
CustomFileEmission mixin in FIRRTL where FIRRTL will no longer delete
emitter annotations.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

* Use CustomFileEmission for ChiselCircuitAnnotation

Removes the explicit chisel3.phases.Emitter and instead does emission
with a CustomFileEmission mixin to ChiselCircuitAnnotation. This then
prevents the need for passing around DeletedAnnotations. As a
consequence, I removed an unnecessary run of a second Converter in the
Driver.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

* Fix tests for use of CustomFileEmission trait

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

* Fixes for newer CustomFileEmission API

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

* Fixed the aspect as parent bug in Data and MonoConnect

* refactored and cleaned up finding an aspect parent

* Added aspect fix to the BiConnect class

* added unit test for manipulating submodules via aspects

* Refactored to move determination of proper parent to Builder and made logic simpler in MonoConnect, Data, and BiConnect

* Removed unused function and provided Scaladoc for retrieveParent

Includes special case support for Counter(0) which has identical
behavior to Counter(1) except for the value of n.

It was private and unused

comment fix only.

* Include and check when scoping as part of reg/mem/wire/node bindings

* Allow outdated 'when' behavior of CHIRRTL memory ports with enables

* Extend cross-module / when-visibility checks to all data refs

* Fixes #1512
* Cannot be checked if outside a module context
* E.g. delayed evaluation of printf / assert args

* Add basic test cases for cross-module refs / signals escaping when scopes

* Remove illegal cross-module references from existing tests

* Added broken auto-clonetype test

* Added bugfix for 2.11

* Add descriptive comment for 2.11 special case

* Update src/test/scala/chiselTests/AutoClonetypeSpec.scala

* Update src/test/scala/chiselTests/AutoClonetypeSpec.scala

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>