Co-authored-by: Jack Koenig <koenig@sifive.com>

* Implement `typeName` API for a few `Data` types

* Fix silly compilation error

* Implement typeName API further for most data types and modules which need it

* Compilation error fixes

* Remove width parameter from Bool

* Test for Queue naming using typeNames

* Remove width-sensitive override for AsyncReset as it is irrelevant

* Add typeName for Analogs

* Add additional types to be tested

* Scalafmt

* Use circt ChiselStage

* Update queue naming of existing tests

* Scalafmt

* Change pipe desiredName to be consistent with other modules

* Update naming cookbook

* Update docs/src/cookbooks/naming.md

Co-authored-by: Megan Wachs <megan@sifive.com>

* Update docs/src/cookbooks/naming.md

Co-authored-by: Megan Wachs <megan@sifive.com>

* Add SInt to TypenameSpec

* Fix cookbook mdoc errors

* compileOnly tag on scala code

* More improvements of mdoc

* compileOnly -> compile-only

* Final mdoc review and fixes

* Add inferred UInt to test

---------

Co-authored-by: Megan Wachs <megan@sifive.com>

Deprecate ChiselStage$.elaborate as this exposes internal Chisel APIs,
namely "chisel3.internal.firrtl.Circuit".  Replace usages of this in
tests with emitCHIRRTL.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

* Change many tests from simulation-based to checking the CHIRRTL.
* Move tests that were hard to convert to new VecIntegrationSpec in
  integration-tests

Co-authored-by: Jack Koenig <koenig@sifive.com>

* mdoc-ify intrinsic explanation

* Update docs/src/explanations/intrinsics.md

* Update intrinsics.md

* IntModule

* intmodule works

* a bit of documentation

* formatting

* example and better test.  Rename all the things, now they are Blue!

* formatting

* typo

* move file

* indexes

* Update core/src/main/scala/chisel3/internal/firrtl/IR.scala

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>

* Update docs/src/explanations/intrinsics.md

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>

* Update docs/src/explanations/intrinsics.md

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>

* simplify tests

---------

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>

Change FIRRTL Circuit conversion/serialization to place
ChiselAnnotations (converted to FIRRTL Annotations) inside the FIRRTL
Circuit and to serialize this using the "%[[]]" inline JSON format that
is present in the FIRRTL spec.  This does not remove _all_ annotations
passed via the annotation file, but it is the first step towards that.

* Add low-level svsim based simulation to Chisel
* Add Peek/Poke API

Introduce `svsim`, a low level library for simulating SystemVerilog using Verilator and VCS. (#3121)

Also run formatting on SBT files.

Directly subclassing Iterable is lazy-ish, but if you call any operation
on the resulting value (eg. map or ++) it will evaluate the Iterable and
return a List.