Deleted a bunch of chiselName and TransitName to get tests to pass because they are hitting the 'you get the same name as the prefix' warnings

* suggestName -- add some runtime deprecations
* suggestName -- make it an error to call suggestName outside of Builder Context
* SuggestName: create an internal version and use it internally to avoid runtime deprecations
* Added a SuggestNameSpec to test suggestName behavior

* Use kebab case for template names

* Add the metadata necessary to pick up the templates:

* added feature request issue template
* added bug report issue template
* Remove old ISSUE_TEMPLATE.md

Co-authored-by: Megan Wachs <megan@sifive.com>

* Delete TransitName and tests
* Add naming tests for Queue and Pipe
* Remove hooks APIs only used by TransitName
* remove stray sbt from comments

Links between markdown pages should not have any file extension to ensure they work on the website.

* Deprecate TransitName
* Add @nowarn macros to usages of TransitName in the repo

Co-authored-by: Jack Koenig <koenig@sifive.com>

This makes it such that we can stop hosting ScalaDoc on the Chisel
website, instead just pointing to the latest docs on javadoc.io

Co-authored-by: Megan Wachs <megan@sifive.com>

Used for separate elaboration of Definition and Instance

Previously, the plugin would crash with a useless internal error.

Define leading '_' as API for creating temporaries

Chisel and FIRRTL have long used signals with names beginning with an
underscore as an API to specify that the name does not really matter.
Tools like Verilator follow a similar convention and exclude signals
with underscore names from waveform dumps by default. With the
introduction of compiler-plugin prefixing in Chisel 3.4, the convention
remained but was hard for users to use unless the unnnamed signal
existed outside of any prefix domain. Notably, unnamed signals are most
useful when creating wires inside of utility methods which almost always
results in the signal ending up with a prefix.

With this commit, Chisel explicitly recognizes signals whos val names
start with an underscore and preserve that underscore regardless of any
prefixing. Chisel will also ignore such underscores when generating
prefixes based on the temporary signal, preventing accidental double
underscores in the names of signals that are prefixed by the temporary.

* Added ImplicitInvalidate trait with tests

BitPat.rawString is called a lot when decoding and is used for certain
BitPat operations. We should use it less but this is at least a bandaid.

Captures default output in TesterDriver with a ProcessLogger using the
Logger from FIRRTL to suppress output from Verilator when running tests.
This will change behavior for any users of the TesterDriver because the
standard out of Verilator compilation and execution is suppressed by default.

Users can create their own ProcessLogger to restore the previous
behavior, eg.

import scala.sys.process.ProcessLogger
val echoLogger = ProcessLogger(Console.out.println, Console.err.println)

Co-authored-by: Jack Koenig <koenig@sifive.com>

Include the function being called in the suggestion.

Remove reflective naming

With reflective naming removed, this warning no longer does anything so
the option to enable it is deprecated.

This includes removal of closeUnboundIds and _onModuleClose which were
hacks to support naming of non-hardware (ie. unbound) Data.

This can result in a substantial performance improvement for large
Modules with many public vals.

This includes both .*Name APIs and .toTarget

Add --warn:reflective-naming

This new argument (and associated annotation) will turn on a warning
whenever reflective naming changes the name of a signal. This is
provided to help migrate from Chisel 3.5 to 3.6 since reflective naming
is removed in Chisel 3.6.

The new function is chisel3.internal.buildName.

Previously, verification statements (assert, assume, cover, and printf)
were only named via reflection.

This is a formatted version of the p"..." interpolator analogous to
Scala's f"..." interpolator. The primary difference is that it supports
formatting interpolated variables by following the variable with
"%<specifier>". For example:

printf(cf"myWire = $myWire%x\n")

This will format the hardware value "myWire" as a hexidecimal value in
the emitted Verilog. Note that literal "%" must be escaped as "%%".

Scala types and format specifiers are supported and are handled in the
same manner as in standard Scala f"..." interpolators.

This includes (and is tested) for both the old .*Name APIs and
.toTarget

ExtModule now uses the same namePorts implementation as regular Modules.
Previously, ExtModules only allowed port naming via runtime reflection.
This meant that .suggestName and other naming APIs do not work. It also
breaks FlatIO for ExtModule which is a potential replacement API for
BlackBox's special `val io` handling.

Co-authored-by: Megan Wachs <megan@sifive.com>

This required implementing _elementsImpl manually for all HWTuple
classes (which do not have the plugin run on them).