- May 30, 2015
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jackbackrack authored
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- May 22, 2015
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jackbackrack authored
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azidar authored
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- May 21, 2015
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azidar authored
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Adam Izraelevitz authored
fix flo writeport emission to new style
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- May 20, 2015
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jackbackrack authored
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jackbackrack authored
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azidar authored
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azidar authored
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azidar authored
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Adam Izraelevitz authored
new flo backend without pads but with generic ops
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jackbackrack authored
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jackbackrack authored
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azidar authored
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- May 19, 2015
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jackbackrack authored
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azidar authored
First pass at a Verilog Backend. Not tested, but compiles and generates reasonable verilog. Requires inlining, future versions will instantiate modules
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azidar authored
Big API Change. Pad is no longer supported. Widths of primops can be flexible, and the output is usually the max of the inputs. Removed all u/s variants, which need to be dealt with in backends where it matters
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- May 16, 2015
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azidar authored
Updated firrtl for its passes to be a bit more modular, and to enable plugging in other backends. Also updated a lot of tests, but not all of them because its annoying.
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- May 15, 2015
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jackbackrack authored
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- May 14, 2015
- May 13, 2015
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jackbackrack authored
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- May 08, 2015
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jackbackrack authored
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- May 06, 2015
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azidar authored
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- May 05, 2015
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azidar authored
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jackbackrack authored
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azidar authored
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azidar authored
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jackbackrack authored
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azidar authored
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azidar authored
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jackbackrack authored
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Adam Izraelevitz authored
firrtl + flo now working with tutorial examples
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azidar authored
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jackbackrack authored
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azidar authored
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- May 03, 2015
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jackbackrack authored
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azidar authored
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azidar authored
Now when expanding ConnectFrom/ToIndex, create a node for the index so it isn't duplicated for all the whens
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- May 02, 2015
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jackbackrack authored
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