Fixed fir files so they correctly compile to verilog! Front-end needs to generate as-SInt instead of convert, always. Added fast build to Makefile

Changed Core.fir so dshl wasn't huge. Fixed padding pass to preserve correct low-firrtl syntax. Generates verilog that compiles, but is not correct

fix pad/trimming pass and fix bits-select width inference bug

Added sequential/combinational memories. Started debugging verilog backend. Added Long support so UInt(LARGENUMBER) works

Added sequential memories. mem no longer exists, must declare either cmem or smem. Added firrtl-gensym utility to generate a hashmap of names

Added external modules. Switched lower firrtl back to wire r; r := Register, instead of using nodes. Added a renaming pass for different backends. This will likely get deprecated, as a more robust name mangling scheme could be needed

fix flo writeport emission to new style

new flo backend without pads but with generic ops

First pass at a Verilog Backend. Not tested, but compiles and generates reasonable verilog. Requires inlining, future versions will instantiate modules