* Partially revert 8e4ddc62

It was an incomplete fix for handling Vec(0).

* Fix assignment from 0-entry Vec: add test

375e2b6a introduced a regression for bundles
containing zero-entry Vecs.  Until zero-width UInts are supported, the
zero-entry Vecs need to be flattened out before doing asUInt/asTypeOf on
a bundle.  Undoing that commit's replacement of Data.flatten with
Aggregate.getElements is the best interim fix.

* still trying to find right mix

* Making some progress on Mux1H

* Mux1H that works in non-optimzed fashion for FixedPoint, works pretty well in general
Catches some additional problem edge cases
Some tests that illustrate most of this

* Moved in Angie's code for handling FixedPoint case
Cleaned up tests considerably, per @ducky64 review

* Just a bit more cleanup

Fixes #554

Using the sample_element of the created wire is incorrect because Wires have no
direction so the Wire constructed for a Vec of Module IO was constructed
incorrectly. Fixes #569 and resolves #522.

Make it relatively easy to override a single CompileOption.

Fixes #567

Creating FixedPoint literals was throwing away width

This caused one hot muxing problems in dsptools
FixedPoint spec fixed based on error uncovered by this change

This also allows asUInt/asTypeOf to work properly on those Bundles,
even though zero-width wire support is lacking.

Use fold(0) instead of reduce to handle the corner case.

Allow muxing FxP of different widths and BPs

* Revert "Change Vec creation to check if gen is lit (and hence needs to be declared)"

This reverts commit dc86e7e1734d6abacb739b488df1de231e6b41b2.
This may address #522 - using chiselCloneType (instead of cloneType) to preserve directionality.

* Add missing implicits to Vec.apply() signature.

* Use correct macro (CompileOptionsTransform) for indexWhere.

This is an odd one.  Using log2Ceil directly results in a Verilator
compile error, presumably due to a FIRRTL zero-width wire bug.

The old implementation failed to check for width <= -2, and
did the wrong thing when -1 was explicitly passed.  Splitting
into two methods avoids the latter issue.

log2Ceil's argument might be 1, so employ a max operator.

Since the argument is at least 2, this change has no semantic effect.

Since the argument is at least 2, this change has no semantic effect.

Both should be zero-width wires.

Provide a better error message when length < 0.

Change log2Up in log2Ceil, which has no effect, since the argument
is always at least 2.

It always should throw an exception when n < 0, but in the specific
case of x.isWidthKnown && x.getWidth == 1, it failed to do so.

This commit also changes log2Up in log2Ceil, which has no effect,
since the argument is always at least 2.

* Use test_run_dir for more tests.

* Use official option and DRY.

Make "test_run_dir" the default for ChiselSpec.
Verify output files are created in DriverSpec tests.

This is necessary for user-defined Record-derived types to retain
the same signal name as they would using a Vec.

Fixes #501. Also added UIntOps test.

Test for ucb-bar/firrtl#407

This turned up after updating #494 (Remove explicit import of NotStrict) and adding the missing implicit CompileOptions to ":="'s signature at which point Scala pointed out FixedPoint's ":=" could not override Data's final ":=" with the same signature: the implicit time bomb.

* Bugfix #513. Needs better test case

* Improved test

* change builder for bundle reflection fix

* fixed bug -- should be not assignable

* Add scaladoc examples for Vec and Bundle

* address comments, added @example tag
eliminate extraneous context

* address comments, added @example tag
eliminate extraneous context

* ok, I've wrestled with the javadoc sytnax, the following commit, is my best result so far

withClockAndReset, withReset, and withClock allow changing the implicit clock and reset.
Module.clock and Module.reset provide access to the current implicit clock and reset.