* Update BoringUtils.bore to not add a port when boring from a port.

When drilling from the original source, if it's already a port, just
use it directly. Added a simple test from this behavior.

Also removed an errant println in the BoringUtilsSpec while updating
it.

Closes https://github.com/chipsalliance/chisel/issues/3401

.

* Updates from PR review.

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Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Also add mill to CI.

[svsim] Don't redirect simulation stderr to a pipe (#3403)

This PR adds new APIs for the SRAM module to instantiate a number of ports connected to individual clocks. This allows the creation of memories driven by multiple clocks, for use cases like clock domain crossover.

This was previously deprecated, and in most cases results in an error
downstream anyway.

It's an error in most cases already, and in the cases it isn't, make it
a warning. Also fix a crash that could occur when viewing a non-Data
containing non-hardware Data.

This is not a functional bug. The recursive form of reify for Element
would use the .topBinding from the wrong argument, so it would recurse
an extra time, but it would ultimately converge to the right value.

5.0.0 is now an official release so i think we should be prompting for different milestones on our PRs

* Avoid emitting 'const const' for const vecs of const elements

* Handle vecs of vecs without intermediate const

* log2 functions
* unsignedBitLength

Change the FIRRTL serializer to use literal identifiers if any identifiers
begin with a leading digit.  This is a FIRRTL 3.0.0 feature that
simplifies parsing.

This enables literal identifier emission anywhere.  However, this code
path is only reachable via MixedVec due to mangling of numeric names to
add a leading underscore in all other circumstances.  In the future, this
commit will enable removing this restriction and switching to literal
identifiers when this happens.

No changes are made to annotation targets.  E.g., the literal identifier,
"wire `42`" in circuit "Foo" and module "Bar" is still referred to by a
local target "~Foo|Bar>42".  This is intentional (for now).  Targets don't
have parsing ambiguity like FIRRTL text and the name of this wire is still
"42" not "`42`".  It follows that the storage of this name in FIRRTL IR is
not changed.  This is the same way that this is handled in CIRCT.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Use new FIRRTL 3.0.0 syntaxes:

  - `a <= b` is now `connect a, b`
  - `c is invalid` is now `invalidate c`
  - a register with a reset is now `regreset`
  - `UInt("b101010")` is now `UInt(0b101010)`

Update the stated version of the FIRRTL emitted to 3.0.0.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

* Fix probe read for bundles

* Remove unwanted commented code

* scalafmt

* Revert Data.scala change

Fixes #3363.

This will speed up the typical test flow by separating the execution
driven tests out.

Also rename the file containing VecIntegrationSpec to match the class
name.

Subclasses of OpaqueType can override errorOnAsUInt to make it an
elaboration time error if .asUInt is called on an instance of the
particular type (including when nested inside of an Aggregate). This
closes a large loophole in the OpaqueType API.

The previous link is no longer working.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
Co-authored-by: Jack Koenig <koenig@sifive.com>

Add a wrapper API around a handful of new CIRCT compiler intrinsics that
allow for FIRRTL inputs to express linear temporal logic expressions and
assert, assume, and cover operations on them. The CIRCT compiler emits
these as SVAs.

Since there are no opaque user-defined types in FIRRTL yet, the
intrinsics all use `UInt<1>` as the type for sequences and properties.
This change exposes a safe Chisel API with `Sequence` and `Property`
wrappers around the internal `UInt<1>` types.

As FIRRTL and the CIRCT compiler evolve, we'll be able to use more
strongly-typed intrinsics and later probably dedicated FIRRTL IR nodes
for this. I also expect the `circt.verif.assert` intrinsics to be
collapsed with the other assertion mechanisms in FIRRTL to provide one
uniform IR node. That's future work though. This commit just gets the
ball rolling.

* Update Chisel Dev Meeting time
* Update some uses of 5.0.0-RC1 to 5.0.0

* Remove support for Scala 2.12

* clean up mill build.

---------

Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

* Allow IntrinsicModule to be used in Instantiate

Change a few `RawModule`s to `BaseModule`s to allow for intrinsic
modules to be used with the instantiation API.

* Add tests for Instantiate of non-RawModules

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Co-authored-by: Fabian Schuiki <fabian@schuiki.ch>