To clean, test, and build Scala 2.11 and Scala 2.12 versions:
  % sbt +clean +test +publishLocal

* Added API to get Verilog from Chisel

* Removed second emitVerilog implementation, added scaladoc

Incorporated suggestions from @edwardcwang

Preprocess chisel3 IR before emission to determing whether
whens have alternatives.

Rest of the binding refactor

Bool implements Reset. Compatibility package includes an implicit
conversion from Reset to Bool.

For a start from a plain Ubuntu you need Java first before sbt

or sbt-scoverage is updated to deal with dependencies.
Unfortunately, enabling this revives the publishing of the coreMacros and chiselFrontend jars and we don't want that.

No functional changes

* Fix style of literal creators
Literal creators for UInt, SInt and Bool were declared with parens, but
virtually all uses of these methods do not use parens.  This is for
issue #539.
This fix is an API breaking change. If anyone has used parens, e.g.
val x = 1.U()
This will now be an error

* remove trailing parens from literal creators in IntegerMathTester

There was a lot of malformed markdown there, this makes it much more readable.

Part 1 of mega-change in #578

Major notes:
- Input(...) and Output(...) now (effectively) recursively override their elements' directions
- Nodes given userDirection (Input, Output, Flip - what the user assigned to _that_ node) and actualDirection (Input, Output, None, but also Bidirectional and BidirectionalFlip for mostly Aggregates), because of the above (since a higher-level Input(...) can override the locally specified user direction).
- DataMirror (node reflection APIs) added to chisel3.experimental. This provides ways to query the user given direction of a node as well as the actual direction.
- checkSynthesizable replaced with requireIsHardware and requireIsChiselType and made available in chisel3.experimental.

Internal changes notes:
- toType moved into Emitter, this makes the implementation cleaner especially considering that Vec types can't be flipped in FIRRTL. This also more clearly separates Chisel frontend from FIRRTL emission.
- Direction separated from Bindings, both are now fields in Data, and all nodes are given hierarchical directions (Aggregates may be Bidirectional). The actualDirection at the Element (leaf) level should be the same as binding directions previously.
- Bindings are hierarchical, children (of a, for example, Bundle) have a ChildBinding that points to their parent. This is different than the previous scheme where Bindings only applied at the Element (leaf) level.
- Lots of small misc clean up.

Future PRs will address other parts of #578, including stricter direction checks that aren't a side-effect of this internal refactor, stricter checks and splitting of binding operations (Wire vs. WireInit), and node operations not introduced here (getType and deprecation of chiselCloneType). Since those shouldn't mess with internals, those should be much smaller.

Also make transform instantiation deterministic

# Conflicts:
#	build.sbt

bump scoverage version

Replace ambiguous bi-connect ("<>") with mono-connect (":=") for internal Pipe wiring.
(cherry picked from commit 0d121a2e)

bump version

Replace ambiguous bi-connect ("<>") with mono-connect (":=") for internal Pipe wiring.

* Update comments describing Decoupled/ReadyValid.
It seems there is a valid use case for EnqIO/DeqIO and updating the comments may clear some of the confusion and encourage their usage.

* Update comments - no functional changes.
Re-flow comments for ReadyValidIO()
Add gen param to DecoupledIO() and IrrevocableIO().

* Update code and comment now that #492 is resolved