Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Fixup and enable Dummy CompatibilitySpec test

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Core deprecation "since" should be "3.2" not "3.3"

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Fix Num.+ Scaladoc

Change Num.+ Scaladoc to state that this is not a growing
addition. Note that this is problematic either way as this macro is
resolved to an abstract method. Classes implementing this typeclass
are technically free to violate what we put in the Scaladoc here.

h/t @kammoh

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Short-term patch to enable this useful behavior. In the future, we may want to rearchitect the type system and/or rethink the more edge-case connect behavior.

* Add width utility functions to avoid incorrect usage of bare log2Ceil().

* Respond to comments:
Remove apply(Data) method.
Change name(s) to signedBitLength, unsignedBitLength.

* Respond to comments - don't be lazy.
Independently calculate the bit length to verify correct operation.

* Respond to comments - return in.bitLength - 0 (not 1) for 0

* Respond to comments - update wdith for signed 0; add explicit tests.

* Add comment expressing zero width wire assumption.

* Use Verilator 4.016
Now that ucbbar/chisel3-tools has Verilator 4.016, use that for tests.

* Update Verilator version in SETUP

function. This also fixes prior issue where ChiselEnums would not
compile when @chiselName was applied to a module containing a ChiselEnum

* First crack at updating the readme
Goals
Include up front example
Simplify
Get users to things quicker
Move complicated details to wiki.

* headers were not working,
intellij and github don't use same render for .md files

* Fix verb agreement

* Add a fir filter diagram
Compact the fir-filter code a bit

* More compact filter

* Additional README.md updates

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

* Don't use chisel-lang.org, drop HCL

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

* Fix link to fir image, make it relative

* Proposed readme changes

* Resize picture, restyle doc bullets

* Added documentation to Decoupled, Conditionals, Counter

* Fixed private Counter class error

* Move Counter class deprecation and re-definition into util package object.

* Revert "Move Counter class deprecation and re-definition into util package object."

This reverts commit f61bdddf7051522363e1d203fcd46b512047c87d.

* Restore the old Counter definition and address this in a separate PR.
We can move the deprecation warning and the type definition into the util package object (see f61bdddf7051522363e1d203fcd46b512047c87d), but then we fail tests using Counter with a `ScalaReflectionException` in Aggregate.scala:779 (in def cloneType) when:
`Some(mirror.reflect(this).symbol)` generates `type Counter is not a class`.

* Made @ducky64 change to Counter doc
Used to generate an inline (logic directly in the containing Module, no internal Module is created) hardware counter.

Chisel stage

This converts the original chisel3.Driver to use
chisel3.stage.ChiselStage. This is implemented in the following way:

  1. ExecutionOptions are converted to an AnnotationSeq

  2. The AnnotationSeq is preprocessed using phases contained in the
     Chisel DriverCompatibility objects. One of these *disables* the
     execution of FirrtlStage by ChiselStage.
  3. ChiselStage runs on the preprocessed AnnotationSeq
  4. The input ExecutionOptionsManager is mutated based on the output
     of ChiselStage.
  5. The FIRRTL stage is re-enabled if it's supposed to run and
     selected FIRRTL DriverCompatibility phases run.
  6. FirrtlStage runs
  7. The output AnnotationSeq is "viewed" as a ChiselExecutionResult

This modifies the original DriverSpec to make it more verbose with the
addition of info statements. The functionality of the DriverSpec is
unmodified.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Adds a method to enable conversion from ChiselExecutionOptions back to
an AnnotationSeq.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

This includes phases necessary to provide backwards compatibility with
the old Chisel3 Driver. These are placed in a DriverCompatibility
object inside chisel3.stage.phases. The following four phases are
included:
  - AddImplicitOutputFile (from a TopNameAnnotation)
  - AddImplicitOutputAnnotationFile phase
  - DisableFirrtlStage (to disable ChiselStage running FirrtlStage)
  - MutateOptionsManager (to update options after ChiselStage)
  - ReEnableFirrtlStage (to renable FirrtlStage if needed)

Additionally, this adds a view of a ChiselExecutionResult for
providing the legacy return type of the Chisel Driver.

Co-Authored-By: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-Authored-By: chick <chick@qrhino.com>
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

This adds ChiselStage, a reimplementation of chisel3.Driver as a
firrtl.options.Stage. This is simplistically described as a pipeline
of Phases.

Co-Authored-By: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-Authored-By: chick <chick@qrhino.com>
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>

Co-Authored-By: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-Authored-By: chick <chick@qrhino.com>
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

This adds an Emitter Phase that writes a ChiselCircuitAnnotation to
a file if a ChiselOutputFileAnnotation is present.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

This coalesces three distinct operations into one Convert Phase:

  1. Chisel Circuit to FIRRTL Circuit (CHIRRTL) conversion
  2. Conversion of Chisel Annotations to FIRRTL Annotations
  3. Generation of RunFirrtlTransformAnnotations

Co-Authored-By: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-Authored-By: chick <chick@qrhino.com>
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

This adds an Elaborate Phase that expands ChiselGeneratorAnnotations
into ChiselCircuitAnnotations and deletes the original.

Co-Authored-By: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-Authored-By: chick <chick@qrhino.com>
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Co-Authored-By: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-Authored-By: chick <chick@qrhino.com>
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Co-Authored-By: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-Authored-By: chick <chick@qrhino.com>
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

This adds the following FIRRTL Annotations to Chisel:

- NoRunFirrtlCompilerAnnotation
- PrintFullStackTraceAnnotation
- ChiselGeneratorAnnotation
- ChiselCircuitAnnotation
- ChiselOutputFileAnnotation

This includes tests for ChiselGeneratorAnnotation as this Annotation
is able to be constructed from a String and to elaborate itself.

Co-Authored-By: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-Authored-By: chick <chick@qrhino.com>
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

* Include snapshots by default in mill.
* Move repositories definition so all modules may use it.

* Minor Scaladoc update
 - add/move package descriptive text
 - fix FixedPoint link (it's chisel3.experimental.FixedPoint)

* Add missing period at EOS