Make assert failures more informative using macros

Add some Chisel2 driver emulation methods

I don't want to have to maintain a big rocket-chip fork to have it run
through Chisel3, so instead I'm adding back some of the driver routines
that existed in Chisel2.

Update README with more architecture details and new testing flow

This allows us to share Verilog test harnesses between the two.

Move firrtl subpackage to inside internal subpackage.

The change to fix elsewhen/otherwise blew up the node count.

Fix when / elsewhen / otherwise behavior and add unit test

Accomplish this by avoiding default-null parameters on the apply methods.

Calling toBits inside of flatten makes asInput/asOutput/asDirectionless fail
on SInts.  Also, the abstract type Data was already defining it to return
Seq[Bits], so this change didn't really change the API.