WIP. Fixed a bunch of tests. Starting on implementing chirrtl, but hit roadblock in assigning clocked ports

Finished supporting nested accesses. Required some nuianced thinking. Pass all feature tests. Deleted CondRead because it tested a problem we don't have any more

Decided to not have Conditionally in low firrtl - instead, Print and
Stop have enables

WIP. Compiles and almost done with verilog backend. Need to think about emitting ports (and the assignments to them)

Lower Types pass. #53

Add a renameall pass that renames nodes according to a user-provided map.

map.

Also rewrite main so stanza and scala passes can be intermixed.

The transformation works! Kind of, it works fine when everything is alwasy ready, has some weird issues when they're not, but also kind of works in that the hardware verifier still reports the right answer, it seems to go to half duty cycle and then do every token twice

Working on generating SimTop, need to figure out how to split the top-level IO between the sim modules.

Everything is broken, need Translator to work on files without a circuit, need to parse queue module text in midas/Utils.scala, need to create (src, dst) -> Module mapping in midas/Fame.scala

Changing simwrapper to group ports that go to different places, not quite there yet. Will allow simple bulk connecting at top-level

In process of adding FAME-1 transformation, updated todos in grammar file, updated Makefile to play nicer when firrtl is a submodule, fixed bug in Translator for single line scopes, fixed firrtl-scala script to point to firrtl.Driver instead of old firrtl.Test