BlackBoxSourceHelper should only run late in compilation to allow
transforms to tweak its behavior (eg. changing BlackBoxTargetDirAnno).

* Add compiler option (`-p`) to emit individual module protobufs
* Implement multi module combination when reading directory of protobufs

Co-authored-by: Jack Koenig <koenig@sifive.com>

We treat it as an assertion that the stop will
never be enabled. stop(0) will still be ignored
(but now demoted to a info from a warning).

* Fix dshl zero-width shift behavior

Add a special case for dshl handling in the ZeroWidths pass.  If one
expression is shifted by a second, zero-width expression, just return
the first expression.  This prevents a bug where the width will
incorrectly expand due to zero-widths introducing a 1-bit zero
expression.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

* fixup! Fix dshl zero-width shift behavior

Uses virtual method .getBytesBuffered: Iterable[Array[Byte]] to optimize
file emission.

* If exist protoc in the $PATH, prefer to using it.

* add checkSystemAntlr4Version and checkSystemProtocVersion

* Update build.sc

Co-authored-by: Jack Koenig <koenig@sifive.com>

Co-authored-by: Jack Koenig <koenig@sifive.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

to make it has the same form with NoDCEAnnotation and NoConstantPropagationAnnotation

This will make it easier for formal verification
libraries to make use of these emitters.

Both transforms are (most likely) not needed.

The SMT backend actually needs to run PropagatePresetAnnotations
(as will treadle at some point).
None of the Verilog specific passes were actually required!

* implement NoCommonSubexpressionElimination to resolve chipsalliance/chisel3#2006

* Update src/main/scala/firrtl/passes/CommonSubexpressionElimination.scala

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Correct incorrect type specified for memories in the FIRRTL
specification.  This is important because the memory type determines
what is a legal bundle to try to connect to a memory port.

I based this off of FIRRTL accepting the following circuit:

    circuit MemOrder:
      module MemOrder:
        input r: {addr : UInt<3>, en : UInt<1>, clk : Clock, flip data : UInt<1>}
        input w: {addr : UInt<3>, en : UInt<1>, clk : Clock, data : UInt<1>, mask : UInt<1>}
        input rw: {addr : UInt<3>, en : UInt<1>, clk : Clock, flip rdata : UInt<1>, wmode : UInt<1>, wdata : UInt<1>, wmask : UInt<1>}

        mem memory:
          data-type => UInt<1>
          depth => 8
          reader => r
          writer => w
          readwriter => rw
          read-latency => 1
          write-latency => 1
          read-under-write => undefined

        memory.r <= r
        memory.w <= w
        memory.rw <= rw

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

This reverts commit 2630537c.

Fix an OG bug where Andr, Orr, and Xorr would accept an arbitrary number
of operands.  Verilog emission doesn't support this and will silently
drop all operands after the first.  E.g., "andr(a, b)" would emit as
"&a".  After this commit, "andr(a, b)" will be rejected by checking
passes.

For archaeological purposes, this appears to have been the behavior
dating back to when this was added in d2d3260a

.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

This has outlived its usefulness.

* rearrange passes to enable optimized firrtl emission

* Support ConstProp on padded arguments to comparisons with literals

* Move shr legalization logic into ConstProp

Continue calling ConstProp of shr in Legalize.

Co-authored-by: Jack Koenig <koenig@sifive.com>

Co-authored-by: Jack Koenig <koenig@sifive.com>

Change the FIRRTL spec to disallow a zero-width multiplexer select.
Clarify that the select line can be either one-bit or zero-bit, but will
infer to one-bit.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

* Add new util "groupByIntoSeq"
* Restore annotation order when dedupping annotations
* Attribute annotations now deduplicate
* Implement doc string anno dedup

Co-authored-by: Jack Koenig <koenig@sifive.com>

* deprecate DependencyAPIMigration.

This will allow chiseltest to save
the hash code to disk for the purpose
of caching simulation binaries.

Add typedef in DependencyManager.

This is a bug fix, before this PR, Scala compiler will infer `Nothing`, which makes code below failed to compile:
```
class UserCompiler extends TransformManager(Seq(Dependency(UserPass))) {
  override def optionalPrerequisiteOf: Seq[TransformDependency] = Seq(
    Dependency[DedupModules]
  )
}
```

* Add transform to deduplicate memory annotations
* Add annotation deduplication to Dedup stage
* ResolveAnnotationPaths and EliminateTargetPaths now invalidate the dedup annotations transform
* Verilog emitter now throws exception when memory annotations fail to dedup

Co-authored-by: Jack Koenig <koenig@sifive.com>

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Update sbt-scalafmt to 2.4.3

Relax spec on 0-bit mux select, use SFC behavior

Change the FIRRTL specification document to allow for 0-bit mux selects.
The existing ZeroWidths pass will promote these to a 1-bit, 0-valued
select signal (which effectively means that the mux can be optimized
away to just the false path).

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>