This adds an apply method to the LogLevel object for conversion from a
String to a LogLevel.value.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Allow the #delay before random initialization to be overridden

The default of 0.002 can be less than the Verilog time precision, which
effectively causes it to be rounded down to 0.  So, allow the user to
`define RANDOMIZE_DELAY to some other value.

If the macro is not defined, the old behavior is preserved.

* Bump to Scala 2.12.6 and make it the default.

* Use Scala 2.11.12 for chisel tests.

* Try with Scala 2.12.4.

- Fixed edge case file name that starts with . and has no suffix

Fixes #780 

  - makes RemoveWires properly include registers in dependency graph
  - adds an apply method to WRef for DefNode
  - adds a test case requiring register reordering

Fixes a bug where registers could be instantiated after nodes that
referred to them

Also add WRef.apply utility for nodes

* Support for load memory annotations in chisel
This PR
 * Delays the BlackBoxSourceHelper transformation to the Emitter stage of the VerilogCompiler
   * remove from VerilogCompiler
   * move to VerilogEmitter
 * Changes the verilog emitter to allow programmatic access to the verilog module declaration
   * Creating a bindable module requires headers to match
 * Provides a unit test that shows how to generate a bindable module.

* Binding support
Treadle needed LoadMemoryAnnotation to be in firrtl instead of chisel in order to recognize the annotations and use them for memory loading

* Binding support
- Fixed bug that handled suffixes on memory initializing files

* Binding support
- Add a bit more doc to the API provided by the VerilogRenderer

* add FoldADD to const prop, add yosys miter tests

* add option for verilog compiler without optimizations

* rename FoldLogicalOp to FoldCommutativeOp

* add GetNamespace and RenameModules, GetNamespace stores namespace as a ModuleNamespaceAnnotation

* add constant propagation for Tail DoPrims

* add scaladocs for MinimumLowFirrtlOptimization and yosysExpectFalure/Success, add constant propagation for Head DoPrim

* add legalize pass to MinimumLowFirrtlOptimizations, use constPropBitExtract in legalize pass

Previously, Vecs of Bundles that contained a zero-width element would
result in a ClassCastException

On circuits with large numbers of width inferences, prepend to a linked
list instead of appending and having to make a copy.

Fixes #842

This caused wrong message: "File a Firrtl Issue"
Instead of the correct "Reference XX is not fully initialized"

[skip formal checks] LEC passes with Formality

* Improve code generation for smem RW-port wmode port

A common case for these port-enables is

    wen = valid & write
    ren = valid & !write

which the RW-port transform currently turns into

    en = (valid & write) | (valid & !write)
    wmode = valid & write

because it proved `wen` and `ren` are mutually exclusive via `write`.

Synthesis tools can trivially optimize `en` to `valid`, so that's not a
problem, but the wmode field can't be optimized if going into a black box.
This PR instead sets `wmode` to whatever node was used to prove
mutual exclusion, which is always a simpler expression.  In this case:

    en = (valid & write) | (valid & !write)
    wmode = write

* In RemoveCHIRRTL, infer mask relative to port definition

Previously, it was inferred relative to the memory definition causing
the mask condition to be redundantly conjoined with the enable signal.

Also enable ReplSeqMems to ignore all ValidIfs (not just on Clocks) to
improve QoR.

Fixes #756

Add support for ProtoBuf serialization and deserialization

* Add support for additional features in .proto description

Features added: Info, Fixed[Type|Literal], AnalogType, Attach, Params

* Add support for .pb input files

This involves an API change where FIRRTL no longer implicitly adds .fir
to input file names

Match https://github.com/freechipsproject/chisel3/pull/783

This fixes --infer-rw to not expect an argument. After the annotations
refactor, no option was required, but some legacy code remained.

This also updates the test cases to be more correct and not specify an
option to --infer-rw.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

* Update Parser to use ANTLR CharStreams

This removes some unnecessary object creation in String reading and
manipulation

* Remove two unnecessary traversals from Block construction in Visitor

Relying on /tmp as a place for test output will fail on multiuser systems and may fail if multiple instances of tests are running for the same user.

Candidate fix for #749
This adds DefRegister netlist ordering to RemoveWires

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

It does not provide anything over NoTargetAnnotation. Its existence
suggests some significance so removing it for clarity.

Escape raw params using \'

Also minor cleanup to literal construction in Visitor

Useful if you want to find out how a node was reachable and you used a blacklist during the reachability analysis

Add optional argument to verilogToCpp to suppress VCD

This enables the pattern of attaching "through" a wire to give better
Verilog that also works in Verilator

Use WrappedExpression when combining attaches in ExpandWhens
to ensure no duplication of references in resulting, combined attaches

Makes ExpandWhens preserve connect Infos
Also fix Travis regressions