Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

This converts the original chisel3.Driver to use
chisel3.stage.ChiselStage. This works in the following way:

  1. ExecutionOptions are converted to an AnnotationSeq
  2. The AnnotationSeq is preprocessed using phases contained in the
     FIRRTL and Chisel DriverCompatibility objects.
  3. ChiselStage runs on the preprocessed AnnotationSeq
  4. The output AnnotationSeq is "viewed" as a ChiselExecutionResult

This modifies the original DriverSpec to make it more verbose with the
addition of info statements. The functionality of the DriverSpec is
unmodified.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Adds a method to enable conversion from ChiselExecutionOptions back to
an AnnotationSeq.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

This includes phases necessary to provide backwards compatibility with
the old Chisel3 Driver. These are placed in a DriverCompatibility
object inside chisel3.stage.phases. The following two phases are
included:
  - AddImplicitOutputFile (from a TopNameAnnotation)
  - Add AddImplicitOutputAnnotationFile phase

Additionally, this adds a view of a ChiselExecutionResult for
providing the legacy return type of the Chisel Driver.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

This adds ChiselStage, a reimplementation of chisel3.Driver as a
firrtl.options.Stage. This is simplistically described as a pipeline
of Phases.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

This adds an Emitter Phase that writes a ChiselCircuitAnnotation to
a file if a ChiselOutputFileAnnotation is present.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

This coalesces three distinct operations into one Convert Phase:

  1. Chisel Circuit to FIRRTL Circuit (CHIRRTL) conversion
  2. Conversion of Chisel Annotations to FIRRTL Annotations
  3. Generation of RunFirrtlTransformAnnotations

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

This adds an Elaborate Phase that expands ChiselGeneratorAnnotations
into ChiselCircuitAnnotations and deletes the original.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

This adds the following FIRRTL Annotations to Chisel:

- NoRunFirrtlCompilerAnnotation
- PrintFullStackTraceAnnotation
- ChiselGeneratorAnnotation
- ChiselCircuitAnnotation
- ChiselOutputFileAnnotation

This includes tests for ChiselGeneratorAnnotation as this Annotation
is able to be constructed from a String and to elaborate itself.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Now that ucbbar/chisel3-tools has Verilator 4.006, use that for tests.

Compatibility for rename introduced by #994

toString on Data subtypes will now print the type and optionally binding information including literals and IO names as feasible.

* Remove GhpagesPlugin. (#966)

* Restore old SCM reference (after removing ghpages)

- Fix BoringUtils deduplication bug, include new tests
- Update/clarify BoringUtils scaladoc

This compresses the Scaladoc for BoringUtils slightly by using 120
character lines and removing unnecessary whitespace.

This also changes the poorly named "dedup" parameter to the what it
actually is: "disableDedup".

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

This adds two tests to the BoringUtilsSpec to explicitly verify that
deduplication is required when boring. This adds tests that both
verify that the test passes as expected with deduplication enabled and
that the same test fails with deduplication disabled.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

This fixes a bug where BoringUtils non-hierarchical sinks would be
deduplicated even when specified that they should not be.

h/t @ucbjrl for discovering this!

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Unify internal (chisel3.core) and external (chisel3 / chisel3.experimental) Module class names (#994)

Fix scaladoc for UInt.unary_!

It performs the operation (x === 0.U), just like in C.   The scaladoc
incorrectly described it as performing the operation !x(0).  (Obviously, these
are equivalent for Bool, but not for UInt in general).

Generate better code for UInt.andR

In the case that the width is known, we can emit one fewer Firrtl node.

This obviously synthesizes the same way, but compiles/simulates faster.