Finally creating a small example that illustrates missing declaration in firrtl file created by using
Vec(n, new EnqIO(new Packet())) along
with EnqIO having initialization code

Added support for finish method of BasicTester to be overridden in a subclass which allows tester to have clean up and other construction code executed after a user code executed during constructor of that subclass

Add Flipped trait; fix DeqIO, this fix looks good to go

If we end up generalizing Strings, this code should be moved elsewhere.

Note FIRRTL doesn't handle this stuff right, so I'm not committing the
companion test yet.

Make assert failures more informative using macros

Add some Chisel2 driver emulation methods

I don't want to have to maintain a big rocket-chip fork to have it run
through Chisel3, so instead I'm adding back some of the driver routines
that existed in Chisel2.

Update README with more architecture details and new testing flow

This allows us to share Verilog test harnesses between the two.

Move firrtl subpackage to inside internal subpackage.

The change to fix elsewhen/otherwise blew up the node count.