new flo backend without pads but with generic ops

First pass at a Verilog Backend. Not tested, but compiles and generates reasonable verilog. Requires inlining, future versions will instantiate modules

Big API Change. Pad is no longer supported. Widths of primops can be flexible, and the output is usually the max of the inputs. Removed all u/s variants, which need to be dealt with in backends where it matters

Updated firrtl for its passes to be a bit more modular, and to enable plugging in other backends. Also updated a lot of tests, but not all of them because its annoying.

Added source indicators from FIRRTL files. Pass in -p i to get them printed. Should show up with check passes

firrtl + flo now working with tutorial examples

Now when expanding ConnectFrom/ToIndex, create a node for the index so it isn't duplicated for all the whens

Fixed performance bug where PlusWidth, MinusWidth, and ExpWidth could be simplified earlier, and also now have equal? defined so mMaxWidth doesn't blow up during width inference