- Nov 22, 2016
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ducky authored
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ducky authored
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Paul Rigge authored
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Paul Rigge authored
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Paul Rigge authored
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Paul Rigge authored
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Paul Rigge authored
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Paul Rigge authored
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Paul Rigge authored
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Paul Rigge authored
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chick authored
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ducky authored
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chick authored
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ducky authored
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ducky authored
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ducky authored
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- Nov 19, 2016
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jackkoenig authored
Also restrict black boxes to not allow hardware inside of them since it was being silently dropped anyway. Resolves #289
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jackkoenig authored
Workaround for: http://www.veripool.org/issues/1101-Verilator-Fix-SmallName-for-ParamTypeDType
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Stevo authored
Also, remove no-longer-special case for n=1.
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Richard Lin authored
Eliminate some doc warnings
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- Nov 18, 2016
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ducky authored
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- Nov 15, 2016
- Nov 03, 2016
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Jim Lawson authored
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Jim Lawson authored
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Adam Izraelevitz authored
Prefix temporary names with underscores so Verilator won't trace them Use verilator argument "--trace-underscore" if you want to trace these signals
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- Nov 02, 2016
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Jim Lawson authored
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- Oct 29, 2016
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Andrew Waterman authored
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- Oct 28, 2016
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Andrew Waterman authored
defaultCompileOptions is convenient, but it frequently foils the compatibility layer by providing strict defaults rather than passing through the user's CompileOptions. This notably manifests for chiselCloneType, which has different behavior for chisel3 and Chisel. Ideally, we'd get rid of defaultCompileOptions within chisel3.core and only supply it to people who import chisel3._ (attn. @ucbjrl). That would statically prevent further regressions of this nature within the core. The change to Vec.truncateIndex seems extraneous, but I chose an alternate implementation rather than requiring compileOptions in another place.
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Andrew Waterman authored
f1507aa7 triggers a rocket-chip regression, because Chisel used to not preserve flippedness on cloneType.
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Donggyu authored
fix SeqMem's read port creation
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Jim Lawson authored
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Jim Lawson authored
Since chisel now depends on firrtl, we need a way for super projects (i.e., rocket-chip) to control the actual firrtl package used by chisel.
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- Oct 27, 2016
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Andrew Waterman authored
No more need for e.g. new Bundle { def foo(dummy: Int): Data } as now you can write new Bundle { def foo: Data } This also removes code duplication with Module. h/t @sdtwigg
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- Oct 26, 2016
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Jim Lawson authored
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- Oct 25, 2016
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Chick Markley authored
* FixedPoint number support for chisel3 FixedPoint numbers have a width and a binary position Either, neither or both maybe inferred. Firrtl will convert these to SInts during lowering passes * Fixes based on Jack's comments on PR #328 * Add experimental warning to FixedPoint class and object * Fixed comment per Adam's comment on PR #328
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Jim Lawson authored
Add a cloneType method to QueueIO
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Jim Lawson authored
Tobits deprecation
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Jim Lawson authored
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- Oct 24, 2016
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Donggyu Kim authored
this helps firrtl to infer read enable signals
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