Loosen restrictions on clocks to enable them to be connected to
DontCare, i.e., be invalidated.

Co-authored-by: Jack Koenig <koenig@sifive.com>
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Co-authored-by: Jack Koenig <koenig@sifive.com>

* Use a single field instead of two in HasId (4-bytes per HasId)
* Set the prefix to Nil after setting ref to free up memory

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Enhance views to [sometimes] support dynamic indexing and implement FlatIO

This is implemented by including any corresponding Aggregates from the
DataView.mapping in the AggregateViewBinding.childMap (which is now of
type Map[Data, Data]).

This enables dynamically indexing Vecs that are themselves elements of
larger Aggregates in views when the corresponding element of the view is
a Vec of the same type. It also increases the number of cases where a
single Target can represent part of a view.

* During sanitize, only filter the String if needed
* Do not recurse on name, saving an unnecessary call to sanitize

This reduces memory use of every HasId by 64 bytes.

Every instance of HasId (including all Data) had 2 ListBuffer vals for
recording post-naming hooks, yet this feature is almost never used.
These are now vars of type List which allows the common case of Nil to
add no incremental memory use per instance of HasId.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

This reverts commit 3c8a810e.

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Also delete an errant println in InstanceSpec

Chisel <> semantics differ somewhat from FIRRTL <= semantics,
so we only emit <= when it would be legal. Otherwise we continue
the old behavior of emitting a connection for every leaf-level
Element.

Co-authored-by: Deborah Soung <debs@sifive.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>

Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
Co-authored-by: Megan Wachs <megan@sifive.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>

* Tweaks to the Verilog-vs-Chisel Page

* Update cookbook.md

* Update verilog-vs-chisel.md

* Update verilog-vs-chisel.md

* Issue errors on out-of-range extracts when width is known

Firrtl will catch this later on, but better to error early if possible.

* Test that errors are generated on OOB extracts when width is known

Co-authored-by: Shola Ogunkelu @Shorla
Co-authored-by: Megan Wachs <megan@sifive.com>
Co-authored-by: Deborah Soung <debs@sifive.com>

Completed as part of Outreachy Internship Dec 2021-March 2022.

Widths are now padded to the maximum width of the inputs.

Co-authored-by: Jack Koenig <koenig@sifive.com>

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

* Only call _elementsImpl once in Bundle.elements

* Distinguish compiler plugin and reflective _elementsImpl

Bundle.elements now will only do post-processing if the user is using
plugin-generated _elementsImpl. This improves performance for the case
where the user does not opt-in to using the plugin to generate
_elementsImpl.

* Change type of Bundle._elementsImpl to Iterable

It was previously SeqMap (ListMap on Scala 2.12). This change gives us
more freedom to optimize the implementation without breaking binary
compatibility. It is scala.collection.Iterable because it is perfectly
fine to return mutable collections (like Arrays) since the only use is
to Iterate on them.

* Disallow users implementing Bundle._elementsImpl

Currently, it would result in a runtime linkage error. This turns it
into a compile-time error.

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Use Builder.deprecated instead of Builder.warning so that the warnings
are aggregated by source locator to prevent spamming the screen with
duplicated warnings.

Warn if clock at memory instantiation differs from clock bound at port
creation and port clock is not manually passed

Co-authored-by: Jack Koenig <koenig@sifive.com>

Adds generation of `Bundle.elements` method to the chores done by the compiler plugin
For each `Bundle` find the relevant visible Chisel field members and construct a
hard-coded list of the elements and their names implemented as `_elementsImpl`

For more details: See plugins/README.md

- Should be no change in API
- Handles inheritance and mixins
- Handles Seq[Data]
- Tests in BundleElementSpec

Co-authored-by: chick <chick.markley@sifive.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>