- Jun 26, 2020
-
-
Schuyler Eldridge authored
This adds three new transforms: - (abstract) LetterCaseTransform parent of case manipulation - LowerCaseNames to lower case all names - UpperCaseNames to upper case all names Signed-off-by:Schuyler Eldridge <schuyler.eldridge@ibm.com>
-
Schuyler Eldridge authored
Signed-off-by:Schuyler Eldridge <schuyler.eldridge@ibm.com>
-
Schuyler Eldridge authored
Signed-off-by:Schuyler Eldridge <schuyler.eldridge@ibm.com>
-
Schuyler Eldridge authored
Add tests for the ManipulateNames transform. Signed-off-by:Schuyler Eldridge <schuyler.eldridge@ibm.com>
-
Schuyler Eldridge authored
Add a new annotation that stores the resulting name of an allowlist name to be manipulated. Signed-off-by:Schuyler Eldridge <schuyler.eldridge@ibm.com>
-
Schuyler Eldridge authored
Rewrite of RemoveKeywordCollisions into a more generic ManipulateNames. The new ManipulateNames transform is abstract in a '(String, Namespace) => String' method that can be used for arbitrary manipulation of names in a circuit. The software architecture remains mostly the same (a rename map is used as the underlying data store). However, the new ManipulateNames used Target as opposed to Named. Add the ability for naming to be selectively enabled or disabled via: - ManipulateNamesAllowlistAnnotation - ManipulateNamesBlocklistAnnotation Signed-off-by:Schuyler Eldridge <schuyler.eldridge@ibm.com>
-
- Jun 25, 2020
-
-
Kevin Laeufer authored
Co-authored-by:mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
-
- Jun 24, 2020
-
-
Jack Koenig authored
If a module has ports of type Bundle that are used in aggregate connections in parent modules, Dedup cannot change the names of the fields of the Bundle or it would change the semantics of the connection. Dedup now detects this case and refrains from agnostifying the ports of such modules to prevent this issue.
-
Tom Alcorn authored
* Add assume, assert, cover statements * Assert submodule assumptions * Add warning when removing verification statements * Remove System Verilog behaviour emitter warning * Add option to disable AssertSubmoduleAssumptions * Document verification statements in the spec The syntax for the new statements is assert(clk, cond, en, msg) assume(clk, cond, en, msg) cover(clk, cond, en, msg) With assert as a representative example, the semantics is as follows: `clk` is the clock, `cond` is the expression being asserted, `en` is the enable signal (if `en` is low then the assert is not checked) and `msg` is a string message intended to be reported as an error message by the model checker if the assertion fails. In the Verilog emitter, the new statements are handled by a new `formals` map, which groups the statements by clock domain. All model checking statements are then emitted within the context of an `ifdef FORMAL` block, which allows model checking tools (like Symbiyosys) to utilize the statements while keeping them out of synthesis flows. Co-authored-by:Albert Magyar <albert.magyar@gmail.com>
-
Jack Koenig authored
-
- Jun 23, 2020
-
-
Schuyler Eldridge authored
Deprecate PreservesAll Trait, Remove Usages
-
Schuyler Eldridge authored
Signed-off-by:Schuyler Eldridge <schuyler.eldridge@ibm.com>
-
Schuyler Eldridge authored
Signed-off-by:Schuyler Eldridge <schuyler.eldridge@ibm.com>
-
Schuyler Eldridge authored
Signed-off-by:Schuyler Eldridge <schuyler.eldridge@ibm.com>
-
Kevin Laeufer authored
* Support Memory Initialization for Simulation and FPGA Flows This adds a minimal annotation that allows users to influence if memories are randomly initialized, if all entries are initialized to the same scalar or if each entry should be initialized to a different value. We use the init block in order to initialize memories which is supported by verilator as well as yosys and has previously been used to randomize the initial memory contents. * LowerTypes: error when trying to split up a memory with MemoryInitAnnotation Currently the MemoryInitAnnotation only works for ground-type memories. We catch misuse of this annotation at the point of the firrtl compiler at which memories on non-ground type get split up, i.e., the LowerTypes transform. Chisel should try to prevent annotating non-ground type memories in the frontend, but it is nice to have an additional check. * MemoryInitSpec: test JSON deserialization * MemoryInitAnnotation: split up into three different annotations instead of exposing MemoryInitValue Co-authored-by:
Albert Magyar <albert.magyar@gmail.com> Co-authored-by:
mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
-
Jiuyang Liu authored
* Add attributes, ifdefs to emitter. * Make ifdef API a little cleaner. * Remove references to ifdefs. * Remove more of the ifdef stuff I missed * Fix up failing tests * Add multiple attribute test case * Remove tpe as a parameter from Annotations. Some general refactoring. * Add some documentation. * Incorporate some feedback * Expand some spaghetti code, add comments * Fix type signature by removing it * bug fix in test * Fix unchecked type parameter matches in AddDescriptionNodes. * use target to replace name Co-authored-by:
Paul Rigge <rigge@berkeley.edu> Co-authored-by:
mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
-
- Jun 20, 2020
-
-
Albert Chen authored
-
- Jun 13, 2020
-
-
Albert Chen authored
* delete usages of toSet for determinism * add formatting suggestion from code review
-
- Jun 12, 2020
-
-
Kevin Laeufer authored
This message informs the user, it does not indicate a failure.
-
- Jun 11, 2020
-
-
Jack Koenig authored
* Build ArrayBuffers in Block.mapStmt * Have empty Block serialize as "skip" The FIRRTL parser requires at least one indented line in each module. Sometimes tests emit and parse modules with no contents; this ensures there's always at least a "skip" in empty modules. Also fix tests that expected certain skips * Use var List as stack in Block.mapStmt impl This replaces Iterator concatenation. In Scala 2.11, RHS recursion on Iterators is not stack safe. This seems to have been fixed in 2.12 by Scala PR 5033. Co-authored-by:mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
-
Jack Koenig authored
-
- Jun 10, 2020
-
-
Jack Koenig authored
Co-authored-by:Schuyler Eldridge <schuyler.eldridge@ibm.com>
-
Jack Koenig authored
This provides a common Python interfaces for monitoring resource usage of subprocesses Co-authored-by:Schuyler Eldridge <schuyler.eldridge@ibm.com>
-
Jack Koenig authored
* Use Travis Workspaces Add stage to build FIRRTL and share it with later steps running the tests * [CI] Do not sbt clean in formal_equiv.sh This change takes advantage of shared workspace in Travis Co-authored-by:mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
-
Jack Koenig authored
-
Jack Koenig authored
Use WrappedExpression instead of MemoizedHash. The benefit of memoizing the hash pales in comparison to the cost of hashing deeply nested Types in the AST. Co-authored-by:Schuyler Eldridge <schuyler.eldridge@ibm.com>
-
- Jun 05, 2020
-
-
Albert Magyar authored
-
Albert Magyar authored
-
Albert Magyar authored
* Switch to more idiomatic flatMap for Utils.expandRef
-
- Jun 04, 2020
-
-
Albert Magyar authored
* Avoid excessively deep recursion * Avoid overhead of DFS for shallow expression trees * Reduce work: skip expressions that cannot contain error-containing subtrees * Review feedback: added commentary to explain new check_widths_e structure
-
Albert Magyar authored
* Extend PassBenchmark to benchmark a particular Pass * Add license note to file
-
- Jun 03, 2020
-
-
Schuyler Eldridge authored
Revert: Generalize keyword collision to name manipulation, Add {Lower,Upper}CaseNames Transforms (#1651) * Revert "Add test of {Lower, Upper}CaseNames" This reverts commit 93c078b8 . Signed-off-by:Schuyler Eldridge <schuyler.eldridge@ibm.com> * Revert "Add --change-name-case <lower|upper> option" This reverts commit d3ab7e2d . Signed-off-by:
Schuyler Eldridge <schuyler.eldridge@ibm.com> * Revert "Add features.{LowerCaseNames, UpperCaseNames} transforms" This reverts commit c8dcdacf . Signed-off-by:
Schuyler Eldridge <schuyler.eldridge@ibm.com> * Revert "Refactor RemoveKeywordCollisions->ManipulateNames" This reverts commit c534c5ab . Signed-off-by:
Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by:
mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
-
Schuyler Eldridge authored
Signed-off-by:
Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by:
mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
-
Schuyler Eldridge authored
Signed-off-by:
Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by:
mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
-
Albert Magyar authored
-
Albert Magyar authored
* This will help encourage use of these rather than WIR
-
Jack Koenig authored
Fix a performance bug in DedupModules introduced in #1539. Stop recalculating the same expensive datastructures for each module, potentially multiple times. Co-authored-by:Schuyler Eldridge <schuyler.eldridge@ibm.com>
-
Jim Lawson authored
-
- May 29, 2020
-
-
Albert Chen authored
- RenameMap Behavior -- Prevent transitive renaming A -> B -> C (continueRenaming) -- Prevent transitive renaming for self-renames - Target -- Override toString as serialize for CompleteTarget -- Expansion of stripHierarchy to enable stripping InstanceTargets to become ModuleTargets Annotations -- Bugfix in extractComponents where Products were not iterated over -- Converts renamed targets to local targets using Target.referringModule to preserve sticky behavior - Eliminate Target Paths -- Make DuplicationHelper use LinkedHashMap, as we iterate over its contents and convert to Seq in def makePathless -- Add DupedResult to map original module to new module targets -- Update renaming to record a map from all relative instance paths to original module, to new module target -- Consumes DedupedResult to give better name to new duplicated module if it was originally deduplicated -- Reorder modules in attempt to preserve original ordering, pre-deduplication -- Move utility functions to object -- Bugfix: add self-renames to prevent ofModule _ of target _ cannot be renamed to Vector(_, _, _, ...) errors - Dedup -- Changed NoDedupAnnotation to contain ModuleTarget, rather than ModuleName -- Added DedupedResult to map original module to the duplicate module -- Consumes DupedResult to pick better name, if it existed -- Updates renaming to chain the following: instancify deduped modules, remap differently named internal signals, then remap AST modules -- Move utility functions to object -- Remove annotations as part of determination of dedup correctness -- Bugfix: add instance renames so that deduped modules have their instances properly renamed - Dead Code Elimination -- Add deletion of ASTModules - Tests -- Morphism Spec to ensure Dedup -> EliminateTargetPaths and EliminateTargetPaths -> Dedup patterns work properly -- Update existing tests to make sure they work properly -- Add Dedup tests to demonstrate instance renaming bug, EliminateTargetPaths for ofModule rename bug, and update RenameMap tests Co-authored-by:
Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by:
Adam Izraelevitz <adam.izraelevitz@sifive.com> Co-authored-by:
Adam Izraelevitz <azidar@gmail.com> Co-authored-by:
Jack Koenig <koenig@sifive.com>
-
- May 27, 2020
-
-
Schuyler Eldridge authored
Change WrappedTransforms to be sensitive to the --class-log-level of their true underlying transform. In effect, information logged in a wrapper (like timing information) will now print as expected. Signed-off-by:Schuyler Eldridge <schuyler.eldridge@ibm.com>
-