Commits · 40bf74bfdf4d07f0d7171b77ae34004eb9c1fa11 · github.com / freechipsproject / chisel3

Aug 26, 2015
- Fixed bug in split expression that leaked connect statements out of a conditional assignment · 40bf74bf
  azidar authored Aug 25, 2015
  
  40bf74bf
- Removed IntWidth, now only use LongWidth. Now do width inference for Constants... · 9fd6d47c
  azidar authored Aug 25, 2015
```
Removed IntWidth, now only use LongWidth. Now do width inference for Constants in parser, and correctly subtract 1 (except when 0) when calculating width from num-bits of BigInt
```
  9fd6d47c
- Added width check pass with tests. #22. · eb1ab67b
  azidar authored Aug 25, 2015
  
  eb1ab67b
Aug 25, 2015
- Temporarily deprecated the flo backend until I fix it · 6cd96b63
  azidar authored Aug 24, 2015
  
  6cd96b63
- Added BigInt error if passed a string without starting with a b or h · b2be9c1b
  azidar authored Aug 24, 2015
  
  b2be9c1b
- Changed all tests to use verilog backend. · 5d3061bf
  azidar authored Aug 24, 2015
  
  5d3061bf
- Removed old chisel3 tests that all failed for syntax reasons. Tests should now... · 50cf7a48
  azidar authored Aug 24, 2015
```
Removed old chisel3 tests that all failed for syntax reasons. Tests should now be small examples, categorized by either passes, errors, or features.
```
  50cf7a48
Aug 21, 2015
- Updated .gitignore · 02a7fb53
  azidar authored Aug 20, 2015
  
  02a7fb53
- Added tests, cleaned up repo · 5694a880
  azidar authored Aug 20, 2015
  
  5694a880
- Added Poison node. Includes tests. #26. · 169164c3
  azidar authored Aug 20, 2015
  
  169164c3
- Added rsh test for const-prop · c50afcbd
  azidar authored Aug 20, 2015
  
  c50afcbd
- Added rsh to BigInt library. Const Prop now works on rsh's on constants. #19. · 5bf451ac
  azidar authored Aug 20, 2015
  
  5bf451ac
- Fixed bigint library to correctly extract bits from UIntValue. #19. · 9175d99c
  azidar authored Aug 20, 2015
  
  9175d99c
Aug 20, 2015
- Added new const propagation test · 2259089f
  azidar authored Aug 19, 2015
  
  2259089f
- Added beginning of constant propagation pass, doesn't work · b6997a24
  azidar authored Aug 19, 2015
  
  b6997a24
- Switched to new bigint library · be50b579
  azidar authored Aug 19, 2015
  
  be50b579
- Check Neg UInt in the parser · 8eec7cf3
  azidar authored Aug 19, 2015
  
  8eec7cf3
- Merge branch 'master' of github.com:ucb-bar/firrtl · b98c9426
  azidar authored Aug 19, 2015
  
  b98c9426
- Fixed width inference bug where constraints were propagating backwards. · 4d4d18a6
  azidar authored Aug 19, 2015
```
Updated tests to match. #29.
```
  4d4d18a6
- Fixed width inference bug where constraints were propagating backwards. Updated tests to match. · 487a6113
  azidar authored Aug 19, 2015
  
  487a6113
Aug 19, 2015
- Updated shr test so it is an expected pass · 51411657
  azidar authored Aug 18, 2015
  
  51411657
- Fixed width inference for static shift left, #18 · f64e4868
  azidar authored Aug 18, 2015
  
  f64e4868
- Fixed verilog emission from rand to random · 9964b8ff
  azidar authored Aug 18, 2015
  
  9964b8ff
- Fixed bug in MinusWidth where it was adding instead of subtracting widths · a27cc1bd
  azidar authored Aug 18, 2015
  
  a27cc1bd
- Fixed so its length is greater than what it connects to. Changed shr to be extract, not >> · 6253cb08
  azidar authored Aug 18, 2015
  
  6253cb08
- Emit random initialization instead of zero initialization for Verilog reg · dc80d4f5
  azidar authored Aug 18, 2015
  
  dc80d4f5
Aug 18, 2015
- Removed leading zeros from UInt constants · 934c9953
  azidar authored Aug 17, 2015
  
  934c9953
- Fixed bug where equality between expressions was incorrect, leading to · 13c6ff8f
  azidar authored Aug 17, 2015
```
an optimization that eliminated some when statements.

Added test case.
```
  13c6ff8f
- Added tests for shl and mem. Fixed bug in verilog output of mem size. · c7e4b472
  azidar authored Aug 17, 2015
  
  c7e4b472
Aug 06, 2015
- Added type inference before gender check · 3cbffd90
  azidar authored Aug 05, 2015
  
  3cbffd90
- Fixed bug in temp elimination. · 8af3f50d
  azidar authored Aug 05, 2015
  
  8af3f50d
Aug 05, 2015
- Added check for reading from outputs with flips · 0ec00323
  azidar authored Aug 04, 2015
  
  0ec00323
- Added () around width printers · ede7df1a
  azidar authored Aug 04, 2015
  
  ede7df1a
- Added verilog keywords to uniquify them · 80846abc
  azidar authored Aug 04, 2015
  
  80846abc
- Fixed reading from instance's input ports. Fixed unique naming bug. · 45a54fad
  azidar authored Aug 04, 2015
  
  45a54fad
Aug 04, 2015
- Changed name mangling to use _ as a delin. Fixed bug in checking for · ff6dfecf
  azidar authored Aug 03, 2015
```
invalid <> assignments.
```
  ff6dfecf
- Added concrete syntax for EmptyStmt() · ec3bf6a6
  azidar authored Aug 03, 2015
  
  ec3bf6a6
- Fixed performance bug in Split Expressions. Changed delin for connect indexed.... · 6f098fb5
  azidar authored Aug 03, 2015
```
Fixed performance bug in Split Expressions. Changed delin for connect indexed. Fixed various broken tests.
```
  6f098fb5
Aug 01, 2015
- Fixed (?) resolve genders pass · 342e7760
  azidar authored Jul 31, 2015
  
  342e7760
- Reading from output ports no longer causes errors · fb625a03
  azidar authored Jul 31, 2015
  
  fb625a03