Introduce `svsim`, a low level library for simulating SystemVerilog using Verilator and VCS. (#3121)

Also run formatting on SBT files.

Directly subclassing Iterable is lazy-ish, but if you call any operation
on the resulting value (eg. map or ++) it will evaluate the Iterable and
return a List.

Co-authored-by: Jack Koenig <koenig@sifive.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Use new private Record._elements to validate Record elements. This
allows us to check invariants earlier than on cloning or binding.

It seems that deprecations on methods that are macro expanded away do
not actually trigger a deprecation warning. Instead, we will just accept
no source locator on the deprecated API (no released version of Chisel
has the source locator).

It is a very painful change for users with marginal benefit. We plan to
change the package to chisel in the not-so-distant future--that's a much
better opportunity to make this change.

* overload MuxLookup.apply for EnumType
* remove MuxLookup.fromEnum
* add source locators to MuxLookup.apply using macros

These annotations are no longer used now that they cannot affect CIRCT
execution.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

* Make read-write inference on by default

Change CIRCT to turn on read-write inference by default.  This is
primarily done because this option was removed in:

  https://github.com/llvm/circt/commit/9620d656f8a59998cc38472a60f83bfdcb6a8549



Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

* Remove IMCP disable option for CIRCT

Remove the ability to disable inter-module constant propagation (IMCP) when
running with CIRCT.  This option was removed in:

  https://github.com/llvm/circt/commit/9620d656f8a59998cc38472a60f83bfdcb6a8549



Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

---------

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

* Emit FIRRTL spec version in Emitter
* Bump FIRRTL spec version to 1.2.0

Change the assertKnownWidth and assertInferredWidth test utility methods
to check Verilog directly as opposed to doing a full Verilator
compilation.  This dramatically improves the speed of these tests and
should help triage failures if there are problems.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Release Chisel v5.0.0-M1

Changes to build.sbt:
* Add developers
* Add ThisBuild / version
* Add organization url
* Simplify pom license and url

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Remove Cat from util

add MuxLookup.fromEnum